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* soc/intel/adl: Set slp-s0 counter frequencyMarx Wang2024-02-231-0/+5
| | | | | | | | | | | | | | | | | System sleep time (SLP_S0 signal asserted) is measured in ticks, for Alder Lake soc in 122us (i.e. ~8197Hz) granularity/ticks. BUG=b:301854636 TEST=/sys/devices/system/cpu/cpuidle/ low_power_idle_system_residency_us" will show system idle residency time Change-Id: I449f7ed0d9ef891ae5266e8fd784a063a75e38eb Signed-off-by: Marx Wang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/alderlake: Remove Alder Lake M SKUSean Rhodes2024-02-225-33/+2
| | | | | | | | | | | ADL-M is not commercially available, so it can be removed. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If769989f7a0434e32ebbcc8eac9b965b70ca71ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/80614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* soc/intel/alderlake: Sync UPD Usb4CmMode with KconfigSean Rhodes2024-02-221-0/+4
| | | | | | | | | | | | | | | The ACPI is adjusted based on SOFTWARE_CONNECTION_MANAGER, so set the UPD to match this to avoid the connection type being mismatched. If it's mismatched, the TBT port will time out. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8a99db165301ce08caf55aac0e33ca1994559d62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80486 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* soc/intel/alderlake: Include ADL-N ID 5Sean Rhodes2024-02-211-0/+2
| | | | | | | | | | This patch adds support for using ADL N 4-core MCH ID 0x4618. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7b9fc64ccf8e2401dcd55607e8f09b348efb3182 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80166 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Include ADL-N ID 5 0x4618Sean Rhodes2024-02-195-0/+6
| | | | | | | | | | This patch adds support for using ADL N 4-core MCH ID 0x4618. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3e4855ce93666c54ab35def9b58e4b13bc9a8672 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* soc/intel/alderlake/acpi: Drop ACPI stub for SATA deviceMatt DeVillier2024-02-182-10/+0
| | | | | | | | | | | This is now generated by acpigen in the common/block/sata module. Change-Id: Ic45a059f47a090aa1993e83884408a82826b30cf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc: Add SPDX license headers to Kconfig filesMartin Roth2024-02-181-0/+2
| | | | | | | | | | Change-Id: Ie7bc4f3ae00bb9601001dbb71e7c3c84fd4f759a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80596 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Leverage IA common code for range calculationsSubrata Banik2024-02-132-126/+4
| | | | | | | | | | | | | | | | Improves code maintainability and potentially reduces redundancy by using the IA common implementation. Additionally, drop the unused macros from SoC local. TEST=Build and boot successful on google/marasov. Change-Id: I290fea99f04cfc9f18e5f1435ed07de42995869f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80403 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cmn/sa: Refactor SA common codeSubrata Banik2024-02-122-13/+10
| | | | | | | | | | | | | | | | | | Leverages common SA header definitions for Host Bridge registers. Renames DSM_BASE_ADDR_REG to BDSM and DPR_REG to DPR for brevity. Additionally, made some minor code alignment corrections while adding newer macros in the header file. TEST= Build and boot successful on google/screebo. Change-Id: I476f213d75a0978336b3749a5ba1499107eb2238 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
* include/device/device.h: Remove CHIP_NAME() macroNicholas Sudsgaard2024-01-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A "good" example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 separate members of the same struct. It was decided to remove this macro altogether, as it does not do anything special and incurs a maintenance burden. Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* soc/intel: Rename Makefiles from .inc to .mkMartin Roth2024-01-242-0/+0
| | | | | | | | | | | | | | | | | | The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib479b93b7d0b2e790d0495b6a6b4b4298a515d9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/80073 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Reland "Kconfig: Bring HEAP_SIZE to a common, large value"Patrick Georgi2024-01-171-5/+0
| | | | | | | | | | | | | | | | | This reverts commit acbc4912375085a099c2427def464d6e481f2a90. Reason for revert: CB:79525 fixes the issue that led to the revert by not maintaining the heap in the SMM-stored copy of ramstage at all. Change-Id: I3c8ef785486d275c9341859d34fce12253bd2bb9 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80023 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Make C1e configurableSean Rhodes2023-12-262-1/+4
| | | | | | | | | | | | | | Make it possible to enable C1e from the devicetree by adding `c1e_enable`. C1e was disabled by ea2a38be323173075db3b13729a4006ea1fef72d for all RPL SOCs to reduce noise. This will ensure that boards that disabled it based on CPUID are unchanged. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I758621393cb39345c2ba7b19a32872e84e1c5a19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77088 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/intel/raptorlake: Updating the FSP v4301.01 headers to Standard pathKulkarni, Srinivas2023-12-141-1/+1
| | | | | | | | | | | Move the existing FSP 4301.01 headers for Raptor Lake out of subdirectory called 43101.01 to follow standard process. Change-Id: I710f373acd37e9e0f8b50084a1a7e9fbda816e8c Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* soc/intel/alderlake: Update LidStatus UPD dynamicallySubrata Banik2023-12-041-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch ensures that the LidStatus UPD is passed a dynamic value, rather than always passing 1 (CONFIG_RUN_FSP_GOP enabled) for FSP 2.0 devices. Problem statement: * FSP-S GFX PEIM initializes the on-board display (eDP) even when the LID is physically closed, because LidStatus is always set to 1. * FSP-S skips external display initialization even when the LID is closed. Solution: * FSP-S GFX PEIM module understands the presence of an external display if LidStatus is not set, and tries to probe the other display endpoint. * Statically passing LidStatus as always enabled (aka 1) does not illustrate the exact device scenarios, so this patch updates LidStatus dynamically by reading the EC memory map offset. BUG=b:313886118 TEST=Able to build and boot google/marasov to redirect the display using external HDMI monitor while LID is closed. Change-Id: Idb1d71bd54837630f36d43a45effc53d35f9cb70 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79352 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Allow using FSP repo for all RPL-S platformsMichał Żygowski2023-11-101-1/+1
| | | | | | | | | | | | | | | The Client FSP for Raptor Lake-S is present on the Intel FSP repository, so there is no need to restrict Raptor Lake-S FSP binary repository to IoT only. TEST=Build and boot MSI PRO Z790-P Change-Id: I77aecd6e2d753732bf6358afe2c7ea0491348387 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-by: Eric Lai <ericllai@google.com>
* soc/alderlake: Fix order of defaults in FSP_HEADER_PATHMichał Żygowski2023-11-101-1/+1
| | | | | | | | | | | | | | | | | | | | The combination of SOC_INTEL_RAPTORLAKE_PCH_S and FSP_TYPE_IOT is currently broken. By default, e.g. for MSI PRO Z790-P, the FSP_HEADER_PATH does not match the default FSP_FD_PATH. For headers the client FSP is selected, while for the FD file, IoT FSP binary is chosen. The order of default for both headers and FD file must be the same to match the headers and binaries. TEST=Build default MSI PRO Z790-P config and see that FSP_HEADER_PATH matches FSP_FD_PATH FSP variant-wise. Change-Id: I8db5ea10c2986ff8d3fa7d616b3f1617d05f0260 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78410 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Revert "Kconfig: Bring HEAP_SIZE to a common, large value"Patrick Georgi2023-11-071-0/+5
| | | | | | | | | | | | | | | | | | | | | | This reverts commit 44a48ce7a46c36df69f7b2cf3552bf10fa5f61b6. Reason for revert: It breaks wakeup from suspend on a bunch of boards. While this approach of eyeballing "correct" values by chipset _should_ be fixed, it should also be accompanied by compile time verification that the memory map works out. Since nobody seems to care enough, let's just revert this, instead of keeping the tree broken for a bunch of configurations. Change-Id: I3cd73b6ce8b15f06d3480a03ab472dcd444d7ccc Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78850 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/alderlake: Add missing min sleep state for DPTF deviceMatt DeVillier2023-11-041-0/+1
| | | | | | | | | | | | | | | | Add an entry in the min_pci_sleep_states array for SA_DEVFN_DPTF, to correct warning in cbmem log: [WARN] unknown min d_state for PCI device 00:04.0 TEST=build/boot google/brya (banshee), verify warning not present in cbmem log, verify entry for DPTF device in ACPI LPI constraint list. Change-Id: I2a9976b065f08e4acd31c3deca13c5278f031a90 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78877 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* drivers/intel/gma/opregion: Use CBFS cache to load VBTJeremy Compostella2023-11-021-4/+0
| | | | | | | | | | | Thanks to x86 CBFS cache support, we can leverage cbfs_map() function to load the VBT binary regardless of if it is compressed or not. Change-Id: I1e37e718a71bd85b0d7dee1efc4c0391798f16f7 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* soc/intel/*: Correct ACPI device name for eMMCMatt DeVillier2023-11-021-1/+1
| | | | | | | | | | | | | | | | | | | | The ACPI name of any device needs to match the name used for generating the S0i3 LPI constraint list, which comes from soc_acpi_name() for each SoC. The names used for the eMMC controller do not match, which will lead to broken ACPI tables since the LPI constriant will reference an ACPI device which does not exist. Some OSes tolerate this better than others, but it should still be corrected. TEST=build/boot google/{hatch,volteer, brya}, dump ACPI and verify no invalid device names referenced. Change-Id: Icbc22b6b2a84bbe73f1b09083f27081612db5eba Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78825 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
* device/device.h: Rename pci_domain_scan_busArthur Heymans2023-10-201-1/+1
| | | | | | | | | | | | | | On all targets the domain works as a host bridge. Xeon-sp code intends to feature multiple host bridges below a domain, hence rename the function to pci_host_bridge_scan_bus. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4e65fdbaf0b42c5f4f62297a60d818d299d76f73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78326 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
* soc/intel/alderlake: Fix incorrect microcode commentsMichał Żygowski2023-10-191-2/+2
| | | | | | | | | | | | | | | | | | | | | The microcode for RPL-S C0 and H0 is actually available, however, the name of the file contained a typo: 06-b7-05 vs 06-bf-05. Fix the typos in the comments. Moreover, the ADL-S C0/H0 microcode file 06-97-05 has the same sha256 sum as the equivalent RPL-S C0/H0 microcode file 06-bf-05. The sha256 sum of ADL-S/RPL-S C0/H0 microcode on intel-microcode tag microcode-20230808: 5d8d4a4d5456c43b7cc04937c80aec094ccbf3bd89f34ffa5182913ef944a9f9 Update the comments to correctly indicate supported CPU steppings. Change-Id: I4c848e0dfc40f6c8e26a9b31e7c4cf4c5a09128f Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78413 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/intel/raptorlake: Use FSP v4301.01 headers for GoogleNick Vaccaro2023-10-191-1/+0
| | | | | | | | | | | | | | | | Remove the existing FSP 4221.00 headers subdirectory called 4221.00_google, and have Google vendor devices use FSP 4301.01. BUG=b:306181828 TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to kernel. Change-Id: Ic64b3aec62f0d6302278393bf06d090f43c0d592 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: <srinivas.kulkarni@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/{adl, mtl}: Avoid redundant display init by joining to MBUSSubrata Banik2023-10-181-0/+1
| | | | | | | | | | | | | | | | | | | | This patch ensures that the IGD joins the MBUS when the firmware splash screen feature is enabled (aka BMP_LOGO config is enabled). For ChromeOS platform, it prevents the i915 driver from reinitializing the display, which can save up to 75ms-80ms of boot time and eliminate a brief period of blank screen between the firmware splash screen and the OS login prompt. BUG=b:284799726 TEST=Able to build and boot google/rex. Change-Id: I36af167afa902053a987602d494a8830ad9b1b1a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* soc/intel/alderlake: Add config for Client RPL FSP supportBora Guvendik2023-10-161-2/+4
| | | | | | | | | | | | For Raptor Lake, select Raptor Lake's .fd file and header. TEST=Boot to OS on Google Brya board with RPL silicon. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ib3172b06b23e19be453142af764dd027bfe8043d Reviewed-on: https://review.coreboot.org/c/coreboot/+/78014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* Kconfig: Bring HEAP_SIZE to a common, large valuePatrick Georgi2023-10-111-5/+0
| | | | | | | | | | | | | | | | | | We have a tiny HEAP_SIZE by default, except when we don't, and mainboards that override it, or not. Since memory isn't exactly at a premium these days, and unused heap doesn't cost anything extra, just crank it up to the highest value we have in the tree by default and remove all overrides. Change-Id: I918a6c58c02496e8074e5fba06e38d9cfd691020 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78270 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel: Select GMA v2 for ADL, MTL, TGL to reflect port/pipe defsSubrata Banik2023-10-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | Intel GFX IP TRANS_DDI_FUNC_CTL register bit definitions have changed since Tiger Lake. This register is used to map ports and pipes to display controllers, so reflecting the correct status is important for detecting physical display end point devices. This patch ensures that ADL, MTL, and TGL SoCs choose GMA version 2 to properly reflect the updated port and pipe register definitions. BUG=b:299137940 TEST=Build and boot google/rex successfully. Change-Id: Ie2082747d18a5f136f410b1019be4d6c801617b1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
* soc/intel: Move USB wake methods to a common ASL fileReka Norman2023-10-043-52/+3
| | | | | | | | | | | | | | | | | | | The ACPI methods for enabling USB wake are identical on ADL, CNL and SKL. Move them to a common ASL file so they can be reused more easily on other SoCs. Also move the USB_PORT_WAKE_ENABLE macro used to create enable bitmasks in devicetree to a common header. BUG=b:300844110 TEST=Use abuild to build kinox, puff, and fizz with and without this change. Check the generated dsdt.aml is unchanged. Change-Id: Iabdfe2bece7fafc284ddf04382f1bbcacc370cce Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* soc/intel/alderlake: Hook up FSP repo for RPL-P/SMatt DeVillier2023-10-031-0/+4
| | | | | | | | | | | | | | | | | Now that Intel has publicly released FSP headers/binaries for RaptorLake-P/S client platforms, set the defaults accordingly if FSP_USE_REPO is not selected. This does not change any existing defaults as the RaptorLake headers in vendorcode are only used when FSP_USE_REPO is not set. TEST=build/boot google/brya (osiris) Change-Id: Ida92d269fcaf6f323599ec174f4dcedbbe65f03c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78190 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* soc/intel/alderlake: Enable LZ4 compression for logo CBFS fileSubrata Banik2023-09-281-0/+3
| | | | | | | | | | | | | | | | | | This patch selects LZ4 decompression for logo CBFS file. Able to save 2ms of the boot time when HAVE_FSP_LOGO_SUPPORT config is enabled. However, the compressed BMP logo size is increased by ~2KB. Raw BMP Image size is ~97KB. BUG=b:284799726 TEST=Able to see pre-boot splash screen while booting google/redrix with 32MB (W25Q256JWEIM) SPI-Flash. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I98e2c9a4f77d0b91f84eda9aec5060b236bd5e94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78121 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Move C State Demotion to mainboard configSean Rhodes2023-09-261-5/+6
| | | | | | | | | | | | Rather than disabling C State demotions for every single Raptor Lake board due to an issue with S0ix, regardless of if they even use S0ix, configure it in the mainboard. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4f941a549bc717ae2f8ec961ead7ac7668347c99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* soc/intel/alderlake: Hook up the OC watchdogMichał Żygowski2023-09-202-0/+4
| | | | | | | | | | | | | | Hook up the OC watchdog common block and initialize it if requested. TEST=Enable watchdog on MSI PRO Z690-A and see the platform resets after some time. Enable the watchdog in driverless mode and see the platform no longer resets and periodic SMI keeps feeding the watchdog. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I1c2c640d48b7e03ad8cd8d6cdf6aac447e93cd86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68945 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel: Update Raptor Lake graphics device IDsBora Guvendik2023-09-181-1/+5
| | | | | | | | | | | | | | | | | | | Added Raptor Lake U graphics device ids. Renamed Raptor Lake U graphics device ids that were marked as Raptor Lake P. Added Raptor Lake P graphics device ids. References: RaptorLake External Design Specification Volume 1 (640555) TEST=Boot to OS Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I44734f927764f872b89e3805a47d16c1ffa28865 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77898 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Remove ACPI_ADL_IPU_ES_SUPPORTJamie Ryu2023-09-161-6/+0
| | | | | | | | | | | | | | | | DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC is added to mipi camera driver to extend the same support for all SoCs, so removing this config from Alderlake SoC code. BUG=None TEST=Build rex and brya to check if the build passes without an error. Change-Id: I5bc23fce89f0ae22b64b90cb12621320cac30d85 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
* vc/intel/raptorlake: Add the FSP v4301.01 headersSean Rhodes2023-09-151-1/+3
| | | | | | | | | | | | | | | | Move the existing FSP 4221.00 headers for Raptor Lake to a subdirectory called 4221.00_google, and select this if the vendor is Google. Add the standard FSP 4301.01 headers to a separate directory, from Intel download #686654, and select this for all other vendors. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Icd99bdee1eeac70dfcaca3d07150d3de6bb83d81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77101 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/{tigerlake,alderlake,meteorlake}: Start to unify the TCSS ACPISean Rhodes2023-09-131-5/+9
| | | | | | | | | | | | | | | The ACPI used for Tiger Lake, Alder Lake and Meteor Lake are very similar, so can be moved to shared code. This commit aligns minor difference between then, such as comments and tabs/spaces. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If6554c7ef9e83740d7ec5dcca6a9d7e32fb182db Reviewed-on: https://review.coreboot.org/c/coreboot/+/77453 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/intel: Move is_tme_supported() from soc/intel to cpu/intelJeremy Compostella2023-09-121-0/+1
| | | | | | | | | | | | | | | | | It makes the detection of this feature accessible without the CONFIG_SOC_INTEL_COMMON_BLOCK_CPU dependency. BUG=288978352 TEST=compilation Change-Id: I005c4953648ac9a90af23818b251efbfd2c04043 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77697 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake_n: Hook up the FSP repositoryFelix Singer2023-09-081-1/+3
| | | | | | | | | Change-Id: I57b54653bd29a728825210403c8f426eb1c9cc48 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* soc/intel/{adl,jsl,mtl,tgl}: Add ACPI name for GNA deviceMatt DeVillier2023-09-011-0/+1
| | | | | | | | | | | | | | Add SA_DEV_SLOT_GNA definition to SoCs missing it, so the name resolves properly. TEST=tested with rest of patch train Change-Id: I31c8b14e5083fc8e212a4e32330125fa72696c73 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/alderlake: add GPIO definitions for RPL PCHTim Crawford2023-08-211-1/+5
| | | | | | | | | | | | The RPL PCH uses a different ACPI Device ID than ADL PCH. Ref: Intel 700 Series Chipset Family PCH Datasheet, Volume 1 (#743835) Change-Id: I03f47a43ff985213ad617e834db7f974f687d877 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* vc/intel/fsp2_0: Add a copy of ADL-S IOT FSP MemInfoHob.h for RPL-S IOTMichał Żygowski2023-08-211-0/+5
| | | | | | | | | | | | | | | | | | Similar situation happened last year when IoT FSP for ADL-S came out before the Client FSP variant: https://github.com/intel/FSP/issues/83 It seems IoT FSP publishes the MemInfoHob.h file much later due to legal reasons. Hack the missing file to get the builds using RPL-S IoT FSP from repo working properly. This change could be merged, subject for later revert (when the header file is published). Change-Id: Iec35db4573a3c3d011e4c1edf1c82a5c34438695 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* soc/intel/alderlake: Guard PchPcie{Clock,Power}Gating on RPL FSPMichał Żygowski2023-08-211-1/+1
| | | | | | | | | | | | | | PchPcieClockGating and PchPciePowerGating UPDs are not yet available in RPL-S IOT FSP. It also looks like those UPDs are not generally available in all public RaptorLake FSP headers yet, so guard it against SOC_INTEL_RAPTORLAKE to avoid build errors. Change-Id: Iedac21bafa3428957e054fc8fefa38f9f776772d Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77337 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* soc/intel/alderlake_n: Allow using the microcode repoFelix Singer2023-08-202-3/+2
| | | | | | | | | | | | Allow users of Alderlake N processors to use the microcode repository and also add their related microcode blob to the list of microcodes which should be included in the coreboot rom. Change-Id: I11c9cb13fa81118bfcb819bad5fb39731c7e3e76 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
* soc/intel/alderlake: Set PchHdaSdiEnable for Alder LakeSean Rhodes2023-08-171-2/+0
| | | | | | | | | | | This UPD does exist for Alder Lake, so set it there also. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If2f405804ab675aaf6dbf8b12d149566055b9eef Reviewed-on: https://review.coreboot.org/c/coreboot/+/77125 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* soc/intel/alderlake: Add provision to show pre-boot splash screenSubrata Banik2023-08-172-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the ability to show a pre-boot splash screen on Meteor Lake systems using FSP-S. The patch calls into `fsp_convert_bmp_to_gop_blt()` when the `BMP_LOGO` config is enabled. This function converts a BMP file to a BLT buffer, which is then used by FSP-S to render the splash screen. Additionally, increase the heap size (malloc'able size) upto 512KB (when BMP_LOGO config is enabled) to accommodate high resolution logo file. BUG=b:284799726 TEST=Able to see splash screen while booting google/marasov with BMP_LOGO config enable. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9f4d1bc0aa991e784624ca19ba96a259ab8ddfa6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/intel/alderlake/chip.h: Use boolean type where applicableMichael Strosche2023-08-161-26/+27
| | | | | | | | Change-Id: If26184058536590b70bbb03209913118307ff6c5 Signed-off-by: Michael Strosche <michael.strosche@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76830 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Remove dummy CPU_SPECIFIC_OPTIONSElyes Haouas2023-08-111-52/+49
| | | | | | | | Change-Id: I83574032ef506a411571e8363f476f322ac13e5e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76686 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Disable PCIe clock gatingPatrick Rudolph2023-08-111-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | Intel requires that all enabled PCIe PCH ports have a CLK_REQ signal connected. The CLK_REQ is used to wake the silicon when link entered L1 link-state. L1 link-state is also entered on PCI-PM D3, even with ASPM L1 disabled. When no CLK_REQ signal is used, for example when it's using a free running clock the silicon will never wake from L1 link state. This will trigger a MCE. Starting with FSP MR4 the UPD 'PchPcieClockGating' allows to work around this issue by disabling ClockGating. Disabling ClockGating should be avoided as the silicon draws more power when it is idle. TEST: Verified on two boards, one with missing CLK_REQ on a PCH root port, that the code does the right decision to disable UPD PchPcieClockGating and PchPciePowerGating when necessary. Change-Id: I673bbdbadc9afbed6a7bd5ce9f35dc70716d875b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Revert "soc/intel/{adl, cmn/pcie}: Fix ASPM configuration enum definitions"Jeremy Soller2023-08-091-7/+12
| | | | | | | | | | | | | | | | | | | | This reverts commit 5dfec718290609dc0fd0331070ad703107e0b7e7. Reason for revert: This change made it impossible to disable ASPM by FSP parameter. ASPM_DISABLE would result in the FSP parameter not being programmed, causing it to be the FSP default value instead. This additionally fixes MTL to match ADL. Change-Id: I60c0ea08513fcb0035449ea3fef1681de528c545 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75280 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-10 14:58:14 +0000