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* soc/intel/tigerlake: Expose In-Band ECC config to mainboardFrans Hendriks2022-08-072-0/+37
| | | | | | | | | | | | | | | | Support for feature "In-Band ECC" not available for Tiger Lake Similar to Elkhart Lake, Tiger Lake also provides this feature. Ported from Elkhart Lake (CB:55668) Bug = N/A TEST = Build and boot Siemens AS-TGL1 Change-Id: Ie54d5f6a9747fad0105d0f8bf725be611bb8cf60 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/acpi: Fix NVJT subfunction IDsTim Wawrzynczak2022-08-071-2/+2
| | | | | | | | | | | | | | | | The POWERCONTROL and PLATPOLICY NVJT subfunctions were incorrectly set to 2 and 3, respectively. While looking at the ACPI code, Nvidia noticed these are supposed to be 3 and 4, also respectively, so this patch fixes that. BUG=b:214581763 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I0f808aba7072b943ee2fad20e06ff39a9b54903d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* commonlib/timestamp_serialized: Add comment explaining "ignore for x86"Reka Norman2022-08-071-0/+8
| | | | | | | | | | | BUG=b:240624460 TEST=None Signed-off-by: Reka Norman <rekanorman@chromium.org> Change-Id: I8542c9bb624a366bc1bb01f6eae66ba97520d19c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66381 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/rex: Add memory config for rexTarun Tuli2022-08-061-2/+57
| | | | | | | | | | | | | Configure the rcomp, dqs and dq tables based on the schematic dated July 17/2022 and Intel Kit #573387. TEST=Built successfully Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I092f42db252052382d377a4ae48dc25f73080a3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66202 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/elogtool: Mark redundant boot mode event type as `deprecated`Subrata Banik2022-08-062-41/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds `_DEPRECATED_` tag to ChromeOS boot mode related event logging types as below: * ELOG_TYPE_CROS_RECOVERY_MODE <---- to record recovery boot reason while booting into recovery mode * ELOG_TYPE_CROS_DEVELOPER_MODE <--- if the platform is booted into developer mode. * ELOG_TYPE_CROS_DIAGNOSTICS <---- if the platform is booted into diagnostic mode. Drop static structure `cros_deprecated_recovery_reasons` as it has been replaced by vb2_get_recovery_reason_string() function. ELOG_TYPE_FW_BOOT_INFO event type is now used to record all those related fw boot info along with ChromeOS boot mode/reason etc. BUG=b:215615970 TEST=Build and boot google/kano to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I932952ce32337e2d54473667ce17582a90882da8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/google/brya/var/vell: Set GPP_B2 NC for RGB keybaordRobert Chen2022-08-051-1/+1
| | | | | | | | | | | | | | | When GPP_B2 output high, there is a leakage path. This patch fix it by setting the pin NC. BUG=b:233959105 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I3c833d5d62c715960dcb27494a0b9b93c91e8f2f Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* vc/intel/fsp/mtl: Update header files from 2253_00 to 2304_01Srinidhi N Kaushik2022-08-052-950/+977
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 2304_01, previous version being 2253_00. FSPM: 1. Removed CpuCrashLogDevice 2. Address offset changes FSPS: Includes below new UPDs 1. VpuEnable 2. SerialIoI3cMode 3. ThcAssignment 4. PchIshI3cEnable BUG=b:240665069 TEST=emerge-rex intel-mtlfsp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I9740e5877af745124d573425da623e814d8df5d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66289 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/mtl: Remove deprecated FSP optionSrinidhi N Kaushik2022-08-051-1/+0
| | | | | | | | | | | | | | | Remove the reference to `CpuCrashLogDevice` UPD since FSP v2304.01 has deprecated this UPD. BUG=b:240665069 TEST=build rex coreboot Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I23223fd7936a60d974229b553de255a7dcf4416b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66357 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/intel/adlrvp: shorten MAINBOARD_PART_NUMBER to fix buildNick Vaccaro2022-08-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Building firmware for Brya is currently broken due to the RO_FWID region for adlrvp_m_ext_ec bloating past 64 characters. The CONFIG_MAINBOARD_PART_NUMBER is catenated onto the CONFIG_MAINBOARD_VENDOR string, which for Intel, makes for a very long trunk string that the kernel version will then be added to form the RO_FWID string. For Intel, that trunk string is already pretty long at : "Intel Corporation_Alder Lake Client Platform". Shortening the CONFIG_MAINBOARD_PART_NUMBER should address this issue for now. BUG=b:241273391 TEST="emerge-brya coreboot chromeos-bootimage" and verify it builds successfully Change-Id: Ie862c87dd9a24743f249f1b10862ca6f3295db23 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
* soc/amd/cezanne/cppc: drop duplicate newlineFelix Held2022-08-041-1/+0
| | | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I774be6d80e0aae725ecb1027501c8d66e0bf5a08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* soc/amd/cezanne/cppc: reduce visibility of cpu_init_cppc_configFelix Held2022-08-042-2/+1
| | | | | | | | | | | | | This function is only called from the same compilation unit, so turn it into a static function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5c2deaa46f69c763df9612e39415b37c60d631be Reviewed-on: https://review.coreboot.org/c/coreboot/+/66398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* mb/google/skyrim: Enable PSP verstageKarthikeyan Ramasubramanian2022-08-031-1/+8
| | | | | | | | | | | | | Enabling required config items to execute verstage in PSP. BUG=b:217414563 TEST=Build and boot to OS in Skyrim with PSP verstage. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Iee14dc80cb6691acb5cb59a21da5a3dff69f7dd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66135 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device: Fix 64Bit Device Resource Info PrintGang Chen2022-08-031-2/+2
| | | | | | | | | | | Use 0x016llx to print device resource info so that both 64bit and 32bit resources could be displayed correctly. Signed-off-by: Gang Chen <gang.c.chen@intel.com> Change-Id: I0ec4c47cca4a09ceb7dc929efaa5630b1f9df81c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* drivers/i2c/dw_i2c: Re-add check for empty i2c transfer listNico Huber2022-08-031-1/+1
| | | | | | | | | | | | | The check was recently removed to allow callers to pass `count == 0`. Dereferencing the `msg` array is invalid in that case, though. Linux, where we borrowed the i2c interface from, also treats this with -EINVAL. Change-Id: I1eec02dd3a3fcf2d477a62cc65292fca40e469d3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tim Crawford <tcrawford@system76.com>
* dev/i2c_bus: Fix `count` argument in i2c_dev_detect()Nico Huber2022-08-031-1/+1
| | | | | | | | | | | | | We actually want the bus driver to process the 1 zero-length write we are passing. So set the count to 1. Change-Id: I5a41abb68c27a83715b6baec91ece9fa90b66a8c Signed-off-by: Nico Huber <nico.h@gmx.de> Tested-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66337 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
* soc/mediatek: Move common definitions to dramc_soc_common.hRex-BC Chen2022-08-034-48/+28
| | | | | | | | | | | | | | Some definitions are the same in dramc_soc.h for MT8192, MT8195 and MT8186, so we move them to dramc_soc_common.h TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I3095333e62abf98de1f2d27033baeeba7a4cad79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66276 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/geralt: Implement SKU ID and RAM codeRex-BC Chen2022-08-033-0/+94
| | | | | | | | | | | | | | | | - Retrieve the SKU ID for Geralt via CBI interface. If that failed (or no data found), fall back to ADC channels for SKU ID. - The RAM code is implemented by the resistor straps that we can read and decode from ADC. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I31626e44bd873a3866c9bd1d511b476737f15a20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66275 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/geralt: Configure GPIOsRex-BC Chen2022-08-033-1/+25
| | | | | | | | | | | | | | | | | | | Configure ChromeOS specific GPIOs: - Open-drain pins to high-z mode: GPIO_EC_AP_INT_ODL, GPIO_GSC_AP_INT_ODL and GPIO_WP_ODL. - GPO mode: GPIO_AP_EC_WARM_RST_REQ, GPIO_EN_SPKR and GPIO_XHCI_INIT_DONE. This patch is based on MT8188G_GPIO_Formal_Application_Spec_V0.3. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I84d3f62ec8a3966fe1982d5d4cf6ff270450d4bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/66274 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/geralt: Configure TPMRex-BC Chen2022-08-034-0/+27
| | | | | | | | | | | | | Initialize I2C bus 1 for TPM control. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: If5807c9bb39260315ecbc55305def483bd2b8c51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66273 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/beadrix: Update SoC gpio pin of DMICTeddy Shih2022-08-031-0/+5
| | | | | | | | | | | | | | | | | | | | Update SoC GPIO setting of unused DMIC channel according to beadrix schematics. GPP_S2 : NF2 -> NC (DMIC1_CLK) GPP_S3 : NF2 -> NC (DMIC1_DATA) BUG=b:203113413, b:237224862 BRANCH=None TEST=on beadrix, validated by beadrix's DMIC working properly. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Ibe2f432cd74b546218ff4ee6e428e9eed9ac611f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/dedede/var/drawcia: Add Wifi SAR for oscinoShon Wang2022-08-031-2/+15
| | | | | | | | | | | | | | | | | | | | Add wifi sar for oscino BUG=b:240373077 BRANCH=dedede TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Cq-Depend: chrome-internal:4893022 Change-Id: I44cbe8ee08d6136ed116623046893c9749795e50 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66176 Reviewed-by: Ivan Chen <yulunchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/dedede/var/beadrix: Update SoC gpio pin of BC1.2Teddy Shih2022-08-032-0/+3
| | | | | | | | | | | | | | | | | | | | Update SoC GPIO setting of adding BC1.2 SLGC55545 according to beadrix schematics. GPP_A18 : NC -> NF1 (USB_OC0_N) BUG=b:214393595, b:226294980 BRANCH=None TEST=on beadrix, validated by beadrix's Type A working properly. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I746931582cc12f49f7f1c667563350ebac8ddfa1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/prodrive/atlas: Select FSP_TYPE_IOTLean Sheng Tan2022-08-031-0/+1
| | | | | | | | | | | Atlas uses IoT FSP. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I4c20600e0b62367e6e58908cf9cf916f309e6362 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com>
* soc/intel/alderlake: Add config for IoT FSP supportLean Sheng Tan2022-08-031-0/+10
| | | | | | | | | | | | | Add new config FSP_TYPE_IOT to add the IoT FSP option so that respective mainboard Kconfig can use IoT FSP if needed. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I01d891348c039269138e64290ae3d6ec75d3c687 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya: Enable DRIVERS_GENESYSLOGIC_GL9755 for kuldaxDavid Wu2022-08-031-0/+1
| | | | | | | | | | | | | Enable DRIVERS_GENESYSLOGIC_GL9755 support for kuldax. BUG=b:232858957 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I1b2c0bff8497d727c697ea6287078055a39bd1f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
* mb/google/brya/variants/agah: set tcc_offset to 3Tony Huang2022-08-031-0/+1
| | | | | | | | | | | | | | | | Set tcc_offset value to 3 in devicetree for Thermal Control Circuit (TCC) activation feature. This value is suggested by Thermal team. BUG=b:240600260 TEST=emerge-draco coreboot verified by thermal team Change-Id: I3044643d52f1d6e883beb3ec87a77f32d086f46c Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* soc/soc/intel: Add UFS device with ref-clk-freq propertyMeera Ravindranath2022-08-034-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UFS storage devices require the bRefClkFreq attribute to be set to operate correctly in high speed mode. The correct value is determined by what the SoC / board supports. For the ADL UFS controller, it is 19.2 MHz. a) Introduce a new ACPI property "ref-clk-freq". b) Add support to configure this property using an SoC Kconfig. Kernel patch: https://web.archive.org/web/20220801060732/https://lore.kernel.org/all/ 20220715210230.1.I365d113d275117dee8fd055ce4fc7e6aebd0bce9@changeid/ BUG=b:238262674 TEST=Build,boot Nirwen and dump SSDT entries and check that the kernel correctly parses ref-clk-freq as 19.2 MHz. Scope (\_SB.PCI0) { Device (UFS) { Name (_ADR, 0x0000000000120007) // _ADR: Address Name (_DDN, "UFS Controller") // _DDN: DOS Device Name Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "ref-clk-freq", 0x0124F800 } } }) } } Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Reka Norman <rekanorman@chromium.org> Change-Id: I80c338a8a61f161b0feb6c5a3ca00cf5e0cfb36c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/amd/sabrina/fch: enable XTAL pad disabling in S0i3Felix Held2022-08-032-0/+2
| | | | | | | | | | | | | | | | | | Switching off the pads of the internal crystal oscillator that connect to the crystal on the board in S0i3 saves a little power, so enable it. No measurements to quantify the power savings have been made. PPR #57243 revision 1.59 was used as a reference. BUG=b:237647468 TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I52f14ae5c614ad8ff0479b619de7164afa1e7648 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66336 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* mb/google/herobrine: Add support to enable displayVinod Polimera2022-08-032-0/+41
| | | | | | | | | | | | | | | This change adds support to enable edp gpios, display init for herobrine. BUG=b:182963902,b:216687885 TEST=Validated on qualcomm sc7280 development board. Monitor name: LQ140M1JW49 Change-Id: I01dbe23afbb3d41d87f24cb7dcfa456cb7f133fb Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64885 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* qualcomm/sc7280: Add support for edp and mdp driverVinod Polimera2022-08-0311-0/+3016
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add support for edp aux read and write. - Update edp panel properties based on edid read. - Configure edp controller and edp phy. Panel details: Manufacturer: SHP Model 1523 Serial Number 0 Made week 53 of 2020 EDID version: 1.4 Digital display 8 bits per primary color channel DisplayPort interface Maximum image size: 31 cm x 17 cm Gamma: 220% Check DPMS levels Supported color formats: RGB 4:4:4 Default (sRGB) color space is primary color space First detailed timing is preferred timing Supports GTF timings within operating range Established timings supported: Standard timings supported: Detailed timings Hex of detail: 5a8780a070384d403020350035ae10000018 Detailed mode (IN HEX): Clock 346500 KHz, 135 mm x ae mm 0780 07b0 07d0 0820 hborder 0 0438 043b 0440 0485 vborder 0 -hsync -vsync Did detailed timing Hex of detail: 653880a070384d403020350035ae10000018 Detailed mode (IN HEX): Clock 144370 KHz, 135 mm x ae mm 0780 07b0 07d0 0820 hborder 0 0438 043b 0440 0485 vborder 0 -hsync -vsync Hex of detail: 000000fd003090a7a7230100000000000000 Monitor ranges (bare limits): 48-144Hz V, 167-167kHz H, max dotclock 350MHz Hex of detail: 000000fc004c513134304d314a5734390a20 Monitor name: LQ140M1JW49 Changes in V2: - Remove Misc delays in edp code. - Move mdss soc code to disp.c - Update EDID read using I2C write & read. Changes in V3: - Remove unrelated delays. - Misc changes. BUG=b:182963902,b:216687885 TEST=Validated on qualcomm sc7280 development board. Monitor name: LQ140M1JW49 Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Change-Id: If89abb76028766b19450e756889a5d7776106f95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
* commonlib: Add support for rational number approximationVinod Polimera2022-08-033-0/+120
| | | | | | | | | | | This patch adds a function to calculate best rational approximation for a given fraction and unit tests for it. Change-Id: I2272d9bb31cde54e65721f95662b80754eee50c2 Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66010 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Configure DDR5 Physical channel width to 64Meera Ravindranath2022-08-021-1/+1
| | | | | | | | | | | | | | | | A DDR5 DIMM internally has two channels each of width 32 bit. But the total physical channel width is 64 bit. BUG=b:180458099 TEST=Boot DDR5 to kernel Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: Ic5e9c58f255bdf86a68ce90a4f853bf4e7c7ccfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/52730 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/dedede/var/pirika: Add Elan touchscreen supportFrankChu2022-08-021-1/+21
| | | | | | | | | | | | | Enable I2C2 and register touchscreen ACPI device for pirika. BUG=b:236564261 TEST=touch screen is functional. Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Id2fd5606b7126eabc1c88bf516198ff00b5d75dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/brya/var/ghost: Enable AMP powerEric Lai2022-08-021-2/+2
| | | | | | | | | | | | | | | Follow latest schematic, GPP_A17 is used to enable AMP power. BUG=b:240006200 BRANCH=firmware-brya-14505.B TEST=Check I2C scan can see the AMP return ACK. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ia6c52302a12ddec68303714ac07e96a65a8f8fb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
* mb/system76: Change touchpad detection methodTim Crawford2022-08-0212-14/+14
| | | | | | | | | | | | | | | | | | Use the new "detect" method instead of "probed". Fixes an uncommon issue where i2c-hid fails to initialize the device on Linux. Tested on: gaze15, gaze16-3060, lemp10, oryp8 Tested: - Linux: Touchpad works across 50 reboots - Windows: Touchpad is still detected as an I2C HID device - Windows: Extra I2C HID devices are not shown in Device Manager Change-Id: I6a899c64a6d77b65a2ae57ab8df81cd84b568184 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/google/geralt: Enable Chrome ECRex-BC Chen2022-08-025-7/+26
| | | | | | | | | | | | | Initialize SPI bus 0 for Chrome EC control. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I6de5ea8a0273a3b0c725e4cdbcf69f4db74c5db7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/intel/alderlake: Add IRQ constraints for CPU PCIe portsTim Crawford2022-08-021-0/+6
| | | | | | | | | | | | | | | | | | | | | | | Copy the constraint from ADL-S to ADL-P. Fixes the following warning in Linux on System76 oryp9, which has an NVIDIA GPU on the bridge. pcieport 0000:00:01.0: can't derive routing for PCI INT A This, in turn, resolves an IRQ conflict with the PCH HDA device that would cause a stack track on every boot. irq 10: nobody cared (try booting with the "irqpoll" option) <snip> [<00000000bf549647>] azx_interrupt [snd_hda_codec] Disabling IRQ #10 Change-Id: I550c80105ff861d051170ed748149aeb25a545db Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66285 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/nissa/craask: Add eMMC DLL tuning valueSimon Yang2022-08-021-0/+45
| | | | | | | | | | | | | | | | Configure eMMC DLL tuning values for Craask board. BUG=b:238985924 TEST="Use the value to boot on Nivviks and Craask successfully." Change-Id: I14f3e2329404cca94e14034d1fb52fcb99a2ddc9 Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66218 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/rex: Enable CSE Lite SKUSubrata Banik2022-08-021-0/+1
| | | | | | | | | | | | | | | The first CSE Lite SKU is available, therefore enable the Kconfig option to have the CSE reboot the system into its RW FW during a cold boot. BUG=b:240228892 TEST=TBD Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I00ef4176cf08cbeed06e446cfe68f06cb1ea27b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66287 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/google/elog: Record vboot FW boot information into elogSubrata Banik2022-08-022-2/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch calls into vboot API (vb2api_get_fw_boot_info) to retrieve FW slot boot information like (tries count, current boot slot, previous boot slot, previous boot status and boot mode). Upon retrieval of the vboot information, elog callback from ramstage records the info into the eventlog. Additionally, this patch refactors the existing event logging mechanism to add newer APIs to record vboot firmware boot related information. BUG=b:215615970 TEST=Build and boot google/kano to ChromeOS and run below command to check the cbmem log: Scenario 1: localhost ~ # cbmem -c | grep VB2 [INFO ] VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0 [INFO ] VB2:vb2api_fill_boot_config() boot_mode=`Developer boot` VB2:vb2api_get_fw_boot_info() fw_tried=`A` fw_try_count=0 fw_prev_tried=`A` fw_prev_result=`Success`. .... Scenario 2: localhost ~ # crossystem recovery_request=1 localhost ~ # cbmem -c | grep VB2 [INFO ] VB2:vb2api_fill_boot_config() boot_mode=`Manual recovery boot` VB2:vb2api_fill_boot_config() recovery_reason=0x13 / 0x00 VB2:vb2api_get_fw_boot_info() fw_tried=`A` fw_try_count=0 fw_prev_tried=`A` fw_prev_result=`Unknown`. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6882cd1c4dbe5e24f6460388cd1af4e4a05fc4da Reviewed-on: https://review.coreboot.org/c/coreboot/+/65561 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/block/apob/apob_cache.c: Add assert for APOB DRAM sizeFred Reitberger2022-08-013-4/+7
| | | | | | | | | | | | | | | | Add static check to ensure the reserved APOB DRAM space is the same size as the MRC_CACHE region specified in the fmap. Update sabrina APOB DRAM size to match the fmap. TEST: Timeless builds identical. Test build with a larger MRC_CACHE than APOB DRAM failed the assert as expected. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia14f6ef94b9062df0612fe96098b1012085ccf9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65878 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/qualcomm: Fill coreboot table with PCIe infoVeerabhadrarao Badiganti2022-08-011-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to pass PCIe base address to payloads, implement pcie_fill_lb() to fill coreboot table with PCIe info. BUG=b:182963902,b:216686574,b:181098581 TEST=Verified on Qualcomm sc7280 development board with NVMe endpoint (Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is getting detected in response to 'storage init' command in depthcharge CLI prompt. Output logs: ->dpch: storage init Initializing NVMe controller 1e0f:0001 Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0 * 0: NVMe Namespace 1 1 devices total Also verified NVMe boot path that is depthcharge is able to load the kernel image from NVMe storage. Change-Id: I1ca2be55b98c8d1b86576072078cdda02ac55940 Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57614 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/herobrine: Add PCIe domain supportVeerabhadrarao Badiganti2022-08-011-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add PCIe domain support for herobrine by enabling it in the devicetree. BUG=b:182963902,b:216686574,b:181098581 TEST=Verified on Qualcomm sc7280 development board with NVMe card (Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is getting detected in response to 'storage init' command in depthcharge CLI prompt. Output logs: ->dpch: storage init Initializing NVMe controller 1e0f:0001 Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0 * 0: NVMe Namespace 1 1 devices total Also verified NVMe boot path, that is depthcharge is able to load the kernel image from NVMe storage. Change-Id: Ied8fbbc8d20698ee081d93ba184b7d0291bb6a76 Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65137 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/qualcomm/sc7280: Enable PCIe driverPrasad Malisetty2022-08-015-1/+287
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable PCIe functionality on sc7280 and supply all the needed data for PCIe generic platform driver. BUG=b:182963902,b:216686574,b:181098581 TEST=Verified on Qualcomm sc7280 development board with NVMe card (Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is getting detected in response to 'storage init' command in depthcharge CLI prompt. Output logs: ->dpch: storage init Initializing NVMe controller 1e0f:0001 Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0 * 0: NVMe Namespace 1 1 devices total Also verified NVMe boot path, that is depthcharge is able to load the kernel image from NVMe storage. Change-Id: I1f79a0ae2dea594d6026d55a15978eeb92a8ff18 Signed-off-by: Prasad Malisetty <quic_pmaliset@quicinc.com> Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66148 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya: Disable the Package C-state demotionZhixing Ma2022-08-011-0/+4
| | | | | | | | | | | | | | | | | | | | Disabling the Package C-state demotion feature for brya baseboard as a work around to the S0ix issue and also this doesn't have any impact on the power and performance measured and verified by the PNP team. This feature will be enabled after its functionality is verified with no issues and also based on its impact on PNP. BUG=none BRANCH=firmware-brya-14505.B TEST=Boot and verified that S0ix issue is resolved. Signed-off-by: Zhixing Ma <zhixing.ma@intel.com> Change-Id: Id3941c8870d41b25488c8ac5d38534fa94664d4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* include: Add SPDX-License-Identifiers to files missing themMartin Roth2022-08-0150-2/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds SPDX-License-Identifiers to all of the files in src/include that are missing them or have unrecognized identifiers. Files that were written specifically for coreboot and don't have license information are licensed GPL-2.0-only, which is the license for the overall coreboot project. Files that were sourced from Linux are similarly GPL-2.0-only. The cpu/power files were committed with source that was licensed as GPL-2.0-or-later, so presumably that's the license for that entire commit. The final file, vbe.h gives a pointer to the BSD-2-Clause license at opensource.org. Change-Id: I3f8fd7848ce11c1a0060e05903fb17a7583b4725 Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* Revert "UPSTREAM: soc/amd/sabrina,vc/amd/fsp/sabrina: Add UART support for ↵Karthikeyan Ramasubramanian2022-08-012-24/+2
| | | | | | | | | | | | | | | | | | | Sabrina" This reverts commit 78261e308de5361b2ff045091e8fb18cad2a5035. Reason for revert: Now that PSP supports a soft fuse flag to toggle the verstage serial logs, prevent PSP verstage from writing to the UART. BUG=None TEST=Build and boot to OS in Skyrim with PSP verstage. Ensure that PSP verstage logs are not seen twice in the console. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I7ef2d585c320ea5903197939136dd2049a71af95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/sabrina: Enable HW Modexp engineKarthikeyan Ramasubramanian2022-08-012-2/+8
| | | | | | | | | | | | | | | | | | HW Modexp engine is verified to be working fine. Any verification failures during PSP verstage are because the firmware body is not read correctly. This might be because of the incorrect SPI ROM mapping. Hence enable the HW modexp engine for keyblock, preamble and firmware body verification. BUG=b:240175446 TEST=Build and boot to OS in Skyrim with PSP verstage using one of the FW slots. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I8f6742630a7049354a24053fce28c477e53259e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* drivers/elog: Use format stringMatei Dibu2022-08-011-1/+1
| | | | | | | | | | | | | | | | | | clang shows the warning below: src/drivers/elog/elog.c:171:13: error: format string is not a string literal (potentially insecure) [-Werror,-Wformat-security] elog_debug(msg); ^~~ Found-by: clang (13.0.1) Change-Id: I3f8949f9ce0c4ef4823530c61c503b0883bb5efc Signed-off-by: Matei Dibu <matdibu@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66262 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* soc/qualcomm: Add PCIe supportPrasad Malisetty2022-07-313-0/+956
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PCIe platform driver for Qualcomm platforms. Reference: - linux/drivers/pci/controller/dwc/pcie-qcom.c - Linux driver base commit: 82a823833f4e3769e82cdb4df1bc2234bc65b16c BUG=b:182963902,b:216686574,b:181098581 TEST=Verified on Qualcomm sc7280 development board with NVMe card (Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is getting detected in response to 'storage init' command in depthcharge CLI prompt. Output logs: ->dpch: storage init Initializing NVMe controller 1e0f:0001 Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0 * 0: NVMe Namespace 1 1 devices total Also verified NVMe boot path, that is depthcharge is able to load the kernel image from NVMe storage. Change-Id: Iccf60aa56541f5230fa9c3f821d7709615c36631 Signed-off-by: Prasad Malisetty <quic_pmaliset@quicinc.com> Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53902 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-11 04:48:13 +0000