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* soc/amd: select RESET_VECTOR_IN_RAM from common non-CAR KconfigFelix Held10 days7-6/+1
| | | | | | | | | | | | | | | | | | | | Select RESET_VECTOR_IN_RAM from the common SOC_AMD_COMMON_BLOCK_NONCAR Kconfig option instead of selecting it in each AMD SoC's Kconfig which selects SOC_AMD_COMMON_BLOCK_NONCAR. From family 17h on, the AMD SoCs don't use cache as RAM (CAR) any more. In most cases, including the coreboot case, the PSP puts coreboot's bootblock into DRAM, thus RESET_VECTOR_IN_RAM needs to be selected. There might be a case where the RESET_VECTOR_IN_RAM part isn't true, but that isn't specific to a SoC generation, so even this unlikely case doesn't prevent us from moving the selection of the Kconfig option to the common non-CAR Kconfig option. Change-Id: I87d7908f94505647f504f9d214e3c52f9c3a3715 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87322 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/uldrenite: Enable ISHYuval Peress10 days2-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Re-enable the ISH for uldrenite and set the correct firmware name. ISH was disabled on uldrenite due to a suspend issue that's no longer there. Uldrenite PoR is to use the ISH. The issue was caused by a bug in Intel's Zephyr HAL which included power management logic that incorrectly handled one of the interrupts. BUG=b:410645679 TEST=ISH device under lscpi. # lspci -s 00:12.0 -knn 00:12.0 Serial controller [0700]: Intel Corporation Device [8086:54fc] Subsystem: Intel Corporation Device [8086:7270] Kernel driver in use: intel_ish_ipc Kernel modules: intel_ish_ipc Change-Id: I567fd43857da0023d063c0bb1b70c206dbee47f4 Signed-off-by: Yuval Peress <peress@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87313 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* mb/starlabs/starbook: Simplify CFR optionsMatt DeVillier10 days3-211/+229
| | | | | | | | | | | | | | Move declaration of all CFR objects to a header file, so they don't need to be guarded. Simplify the enablement of CFR options by creating board-level Kconfig options as needed. TEST=build/boot starbook MTL, TGL, ADL-N. Change-Id: I43dfa6795708e9975b938ce1359629f6b9c4f1cf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* mb/amb/crater: Clean up port descriptorsAna Carolina Cabral11 days1-32/+36
| | | | | | | | | | Use defines to create dxio descriptors as other mainboards. Change-Id: I09e8a9fc37a7b775b76a3d8e5faaee7828f99000 Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87220 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne: Add DPTC supportAna Carolina Cabral11 days1-0/+7
| | | | | | | | | | Add support for DPTC by calling SB.DPTC() as part of PNOT(). Change-Id: I29d7177c96217bf03eaea818cfc1f944f4e640a6 Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87218 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/amd/crater: Enable CPPC supportAna Carolina Cabral11 days1-0/+8
| | | | | | | | | | Enable CPPC configuration in mainboard devicetree. Change-Id: Ifbe65db23aff932ceb92861426fda9358cd655be Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87217 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/nissa/var/guren: Add SPD ID for H58G56CK8BX146Brian Hsu11 days3-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Support memory of SK-hynix H58G56CK8BX146 in mem_parts_used list, and generate SPD ID for this part. DRAM Part Name Vendor Model Spec ID to assign H58G56CK8BX146 SK hynix LPDDR5X 8533 32Gb 6 (0110) BUG=b:409971450 BRANCH=firmware-nissa-15217.B TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\ part_id_gen.go ADL lp5 \ src/mainboard/google/brya/variants/guren/memory/ \ src/mainboard/google/brya/variants/guren/memory/\ mem_parts_used.txt" Change-Id: I4616b44a164391d7a14cc97efb059e731d35c308 Signed-off-by: Brian Hsu <Brian_Hsu@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87275 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Brian Hsu <brian_hsu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
* soc/amd/mendocino/Makefile.mk: Fix syntax with trailing "/"Maximilian Brune12 days1-2/+2
| | | | | | | | | | | It doesn't cause any problems, because the next line is empty. But it is wrong nonetheless. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I8f1e99e06575e769f5698e4cd86e44f0b4df8a07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/87289 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/nissa/var/meliks: Get wifi sar nameSeunghwan Kim12 days3-0/+10
| | | | | | | | | | | | | | | Add get_wifi_sar_cbfs_file_name() to return to wifi SAR file name. BUG=b:404374545 TEST=FW_NAME=meliks emerge-nissa coreboot Change-Id: I2d7a08059c0ed7588311a421faf59146ac43001d Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
* mb/google/fatcat/var/felino: Use GPP_E03 for EC_SYNC_IRQTongtong Pan12 days2-3/+3
| | | | | | | | | | | | | | | | | | Use GPP_E03 as the EC sync interrupt and provide this value to the embedded controller to be exported to the OS. BUG=b:403383143 Test=emerge-fatcat coreboot and Confirm the log: cros_ec_lpcs GOOG0004:00: Chrome EC device registered Change-Id: If7d120fcf2de8dbbbc399d2ead4e294d11ea8a14 Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87210 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
* mb/google/nissa/var/dirks: Enable ASPM of RTL8111HDavid Wu12 days1-0/+1
| | | | | | | | | | | | | | | | | | Because the NIC does not enter ASPM L1.2. Here we add "enable_aspm_l1_2" in overridetree for RTL8111H. BUG=b:407469351 TEST=emerge and test with command powerd_dbus_suspend. Check firmware log output [INFO ] rtl: Enable ASPM L1.2 Change-Id: I0e4f0a4aba736811f3b803f4a1245a635ec59407 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87232 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* mb/google/fatcat/var/felino: fix DMIC1 recordingMac Chiang12 days1-2/+2
| | | | | | | | | | | | | | | | | | | According to the PTL GPIO implementation summary document, NF2 is a null function pin. Correct to NF3 for DMIC_CLK_A1 and DMIC_DAT_A1 function pins. BUG=b:378629979 Test=emerge-fatcat coreboot Verify DMIC recording functionality. Command: arecord -D hw:0,10 -r 48000 -c 4 -f s32 dmic.wav Signed-off-by: Mac Chiang <mac.chiang@intel.com> Change-Id: Ic73b43e6d58376e0c592ef4a1a9c9d9fc7e66928 Reviewed-on: https://review.coreboot.org/c/coreboot/+/87237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
* soc/qualcomm/common: Avoid hardcoding SPI bus from QUP rangeSubrata Banik12 days1-1/+2
| | | | | | | | | | | | | | | | | The `spi_ctrlr_bus_map` defines the range of SPI bus numbers managed by different controllers. Previously, the generic `spi_qup_ctrlr` was hardcoded to manage buses 0 through 15. Modify the `.bus_end` value for the `spi_qup_ctrlr` entry to be `QUPV3_SE_MAX - 1`. TEST=Able to build google/herobrine. Change-Id: I7e9ec555a6d72d93bc23285e48eab52030978e1a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* soc/amd/*/i2c: add missing iomap.h includeFelix Held12 days5-0/+5
| | | | | | | | | | APU_I2C*_BASE are defined in the SoC's iomap.h, so include it. Change-Id: Id7b1674914a045699d6df53b20e35028c3936f67 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87281 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/elkhartlake/pmc,gpio: Fix PMC GPE GPIO routesMichał Żygowski12 days3-13/+10
| | | | | | | | | | | | | | | | | | Based on the description of PMC GPIO_CONF register from EHL EDS Vol 2 Book 2 rev 2.3 #614109. Some of the groups had incorrect values or even defined non-existent GPIO groups. TEST=Boot Protectli VP2420 to Ubuntu 24.04. Change-Id: I910f3c4c0d31b8d24b83cd2c3a28688b898b5d9f Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87050 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
* Revert "src/cpu,soc/amd/common/block/cpu: Add preload_microcode"Maximilian Brune13 days3-19/+0
| | | | | | | | | | | | | | | This reverts commit 4b5a490b6f3faffe1880c731b50d1a4adabfb622. Reason for revert: This effort was apparently given up on since 4 years. So remove the function, since it is not used at the moment. If someone wants to bring that effort back to live, said person can feel free to do so. Change-Id: I26d5c9fbfd6eae24f876d857a6e952ca0d1a64ae Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* Revert "acpi,Makefile: Add preload_acpi_dsdt"Maximilian Brune13 days2-12/+0
| | | | | | | | | | | | | | | This reverts commit 6b446b991b00c44902b70d86c75b23a8f93d510b. Reason for revert: This effort was apparently given up on since 4 years. So remove the function, since it is not used at the moment. If someone wants to bring that effort back to live, said person can feel free to do so. Change-Id: Ifa1ca58c8bf6aabb5b291d3244b1a1a0a7aec6c7 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87065 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/pci_ids: Add Raptor Lake P root port IDHarrie Paijmans13 days2-0/+2
| | | | | | | | | | | | | | | | Add Raptor Lake P specific PCIe root port ID. Based on intel document 640552 rev 2.81. BUG=NA TEST=Customer platform with Raptorlake-P Change-Id: Ifa7c131b5ae47294c055b9e68dad2764607c032b Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87244 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
* mb/starlabs/starbook/tgl: Correct GPIO configsSean Rhodes13 days1-6/+6
| | | | | | | | | | | | | | Several pads were not configured or configured incorrectly. FSP was correcting them, but adjust the config in coreboot so this is not necassary. The config aligns with all other Star Labs boards. Change-Id: Id41ea5d2f4f4321526d25b27411dad02fbde90b6 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87261 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/starbook/tgl: Disconnect unused GPIOsSean Rhodes13 days1-134/+2
| | | | | | | | | | | | Configure pads that aren't connected to anything to PAD_NC. Also, remove comments for these pads. Change-Id: Iaee9f3fc5639d5147f5bdf45fb5311a0121e2c78 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87260 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/starbook/tgl: Move webcam GPIO to it's own groupSean Rhodes13 days1-2/+3
| | | | | | | | Change-Id: I88fa42782e4f262f6595bb6394f21f65bb3c1b21 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/starbook/tgl: Reconfigure PCH Strap GPIOsSean Rhodes13 days1-24/+14
| | | | | | | | | | | | | Configure all strap GPIOs as outputs, rather than some being not connected. This doesn't change anything, but is more explicit. Set these all to sample on RSMRST. Change-Id: I944744f103aa2d1c347856a059d3dd6231b219c4 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/intel/ptlrvp: Update flashmap to allocate 14MB to BIOSJamie Ryu13 days1-9/+5
| | | | | | | | | | | | | | | | | | | This updates the Flashmap (FMAP) descriptor to allocate 18MB to Silicon Management Engine (SI_ME) and 14MB for BIOS. Panther Lake (PTL) Reference Validation Platform (RVP) coreboot is used with several types of RVP boards, and this layout with a 14MB BIOS is very convenient for debugging and creating coreboot for certain use cases and testing purposes. TEST=Build the ptlrvp variant (ES) and check if the flashmap of the coreboot is updated correctly. Change-Id: Ie85b79ae8f7d4e30cf48eb6301224b0cf01b8dff Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87035 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
* soc/intel/alderlake/vr_config: Add i7-1370PEHarrie Paijmans13 days1-1/+5
| | | | | | | | | | | | | | | | | Add the Raptorlake-P/H/H Refresh (6+8)(28W) with MCH_ID 0xa706 to the vr_config table. BUG=NA TEST=Customer platform with Raptorlake-P Change-Id: Iabc668e81596b136470cbe2a1c84f8f53403448f Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87245 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
* device/pci_ids: Add Amston Lake CPU IDsHarrie Paijmans13 days6-0/+26
| | | | | | | | | | | | | | | | Intel processor number X7433RE. Based on docs 721616 rev 2.3. BUG=NA TEST=Boots on Intel Alder Lake CRB with X7433RE processor Change-Id: Ia43945887e7d536b5b7387a4dda4e245973c27ee Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
* superio/fintek: Add support for f81966dHarrie Paijmans13 days10-0/+575
| | | | | | | | | | | | | | | | | | | This patch adds support for the Fintek f81966d SuperIO, which is very similar to the fintek/f81866d. Datasheet: - Name: F81966D/A, Release Date: Oct 2023, Version: V0.21P BUG=NA TEST=Customer platform with F81966D, verified with 'superiotool -de' Change-Id: Ibe3987b6e15eb07b92d7f5a7de2bd511de85e2f7 Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87198 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
* superio/fintek/f81866d: Undo set config mode for HWMMaxim Polyakov13 days1-4/+0
| | | | | | | | | | | | | | | The hardware monitor provides access to its address space via the base address stored in LDN 0x4 at index 0x60/0x61. There is no need to set the configuration mode here, since the registers in the LDN are not programmed. Change-Id: Ic27c9eee5a58727a70fc0ebe60a643f45a418d36 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* superio/fintek/f81866d: Fix HWM port addressMaxim Polyakov13 days1-16/+16
| | | | | | | | | | | | | | | | | | | | | | | The HWM port is +5 to the base address stored in LDN 0x4 at index 0x60/0x61. Take this rule into account when configuring the monitor, as it was done for Fintek SIO chips in the superiotool utility [1]. [1] commit d92745b TEST=Run coreboot on the motherboard with the Fintek F81966 chip (which is architecturally compatible) with pnp_write_hwm5_index() in the HWM initialization code: - the fans are regulated correctly; - superiotool prints the values of the configuration registers updated during initialization. Change-Id: If39400e56a7d0792a5bc8f312c29dd5e98a0b2d3 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87273 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Harrie Paijmans <hpaijmans@eltan.com>
* soc/amd/*/include/aoac_defs.h: add I3C controller AOAC IDsFelix Held13 days4-0/+16
| | | | | | | | | | | | | | | | | | Add the AOAC IDs of the I3C controllers. The following documentation was used to verify this: Genoa: #55901 Rev 0.40 Mendocino: #57243 Rev 3.08 Rembrandt: #56558 Rev 3.09 (in Mendocino directory) Phoenix: #57019 Rev 3.09 Glinda: #57254 Rev 3.00 Faegan: #57928 Rev 1.51 (in Glinda directory) Change-Id: I54d049c58756251506f94d220e1970ccec170918 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87279 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd: report I3C controller MMIO to resource allocatorFelix Held13 days13-24/+47
| | | | | | | | | | | | | | Add minimal common AMD I3C controller code that reports the MMIO region used by the different I3C controllers to the resource allocator. For this to work, select the introduced SOC_AMD_COMMON_BLOCK_I3C Kconfig option and add the 'soc_amd_i3c_mmio_ops' device operations to the I3C device devicetree entries on all SoCs that include I3C controllers. Change-Id: Iebf709d2548f2535b2a2a03a4f6da9531559c238 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
* soc/amd: add I3C controller base addresses and devicetree entriesFelix Held13 days8-0/+35
| | | | | | | | | | | | | | | | | | | | | Add the base addresses of the I3C controllers and the mmio devices to the devicetree for the SoCs that have I3C controllers. The following documentation was used to verify this: Mendocino: #57243 Rev 3.08 Rembrandt: #56558 Rev 3.09 (in Mendocino directory) Phoenix: #57019 Rev 3.09 Glinda: #57254 Rev 3.00 Faegan: #57928 Rev 1.51 (in Glinda directory) For Genoa, those entries already existed in both its iomap.h and its devicetree. Cezanne and Picasso don't have I3C controllers. Change-Id: I6e8073e6498266b909b6cc5f589353f2ed23a62f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87276 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne: Enable system wake up from ACPI S3 using USB keyboardAnand Vaikar13 days2-1/+6
| | | | | | | | | | | TEST: Tested by entering ACPI S3 sleep state and pressing any key on USB keyboard wakes up the system. Change-Id: Ieed635a7199f53c2e7c69c8f17b3ef50b76b8d91 Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87287 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/block/spi: Enforce default ROM mappingPatrick Rudolph13 days1-0/+8
| | | | | | | | | | | | Make sure that the ROM2 MMIO area starts at flash address 0. Document 56780 Change-Id: I1fc06517ea496441147375579800f7349e39facc Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/common/block: Read SPI rom remappingPatrick Rudolph13 days2-0/+18
| | | | | | | | | | | | | | | | | | | | When a SPI ROM greater than 16MByte is being used it will be split into 16MByte chunks that can be remapped in HW as an automatic recovery mechanism. As an example when the EFS in the first 16MByte is corrupted and the second 16MByte EFS is valid the HW will switch pages. The automatic address translation of the MMIO ROM needs to be accounted when accessing the ROM2/ROM3 BAR. Add a function to retrieve the current address remapping and print it in show_spi_speeds_and_modes() for debugging purposes. Document 56780 Change-Id: I046e029e6135ab57f79b675c62b233203f00d705 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87175 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8196: Add validity check for PI_IMGYu-Ping Wu13 days1-0/+9
| | | | | | | | | | | | | | | | Call check-pi-img.py to perform validity check for the PI_IMG firmware file. BUG=none TEST=emerge-rauru coreboot TEST=cbfstool coreboot.rom print | grep pi_img BRANCH=rauru Change-Id: I7b8085c1229c1a7a8cad904e166471ff8bda5cfb Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86352 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/nissa/var/anraggar: Support x32 memory configurationQinghong Zeng13 days4-0/+27
| | | | | | | | | | | | | | | | Use GPP_E19 level to determine whether x32 memory configuration is supported. BUG=b:409212348 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ic401d3db57659c6ced13c123591c1fd82fa9a721 Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
* mb/google/nissa/var/teliks: Support x32 memory configurationQinghong Zeng13 days4-0/+27
| | | | | | | | | | | | | | | | Use GPP_E19 level to determine whether x32 memory configuration is supported. BUG=b:409212347 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I152501858069b5164e8ea602373ed27a5288acb1 Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87233 Reviewed-by: Jayvik Desai <jayvik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* mb/google/nissa/var/telith: Support x32 memory configurationKun Liu13 days4-0/+27
| | | | | | | | | | | | | | | | | Use GPP_E19 level to determine whether x32 memory configuration is supported. BUG=b:405303038 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I969fea2aba858f76870c1a31ad4bd884ec9b6ff3 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87212 Reviewed-by: Jayvik Desai <jayvik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
* mb/google/nissa/var/glassway: Support Memory Hynix H58G56CK8BX146Daniel Peng13 days3-2/+5
| | | | | | | | | | | | | | | | | | | | | Add the new memory support: Hynix H58G56CK8BX146 BUG=b:404452285 BRANCH=firmware-nissa-15217.B TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\ part_id_gen.go ADL lp5 \ src/mainboard/google/brya/variants/glassway/memory/ \ src/mainboard/google/brya/variants/glassway/memory/\ mem_parts_used.txt" Change-Id: I1d6bbb778e75f6f32012e0cf6f427101d3616246 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87252 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
* mb/google/brya/var/guren: Add Stylus Pen FunctionDaniel Peng13 days3-4/+32
| | | | | | | | | | | | | | | | | | | | New Stylus Pen for MAXEYE/0585501490 module for Guren360 project. 1. Add STYLUS fw_config setting 2. Enable stylus device settings 3. Disable the stylus GPIO pins based on fw_config BUG=b:406168542 BRANCH=firmware-nissa-15217.B TEST=1. emerge-nissa coreboot 2. Confirm command evtest for stylus PRP0001:00 and workable. Change-Id: I46d679d29b35d0f4fc70d63b74975d3bdfc40b7b Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87235 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/nissa/var/guren: Add touch screen FTSC1000 supportBrian Hsu13 days1-0/+20
| | | | | | | | | | | | | | | | | | | New Touchscreen function for Guren project. Touchscreen panel: HKO RB116AS01-2, and set TOUCHSCREEN_FTSC1000 to value "3". BUG=b:391281767 BRANCH=firmware-nissa-15217.B TEST=1. emerge-nissa coreboot chromeos-bootimage 2. Confirm command evtest and touchscreen function is workable. Change-Id: Icfe5f57c69d1bd98e0852a1aa3baed8c1444e4d9 Signed-off-by: Brian Hsu <Brian_Hsu@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87238 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/pantherlake: Remove implicit VBOOT_MUST_REQUEST_DISPLAY selectionSubrata Banik2025-04-121-1/+0
| | | | | | | | | | | | | | | | | | | | The explicit selection of `CONFIG_VBOOT_MUST_REQUEST_DISPLAY` for Panther Lake SoC has been removed. Panther Lake platforms inherently enable display across all boot modes (normal, developer, recovery) when vboot is active. Therefore, explicitly selecting `VBOOT_MUST_REQUEST_DISPLAY` becomes redundant, especially when `VBOOT_ALWAYS_ENABLE_DISPLAY` is enabled due to the selection of `BMP_LOGO` for ChromeOS devices. TEST=Able to perform ec sync without any additional reboots. Change-Id: Ifa222d6910664a22eacdb6fea54e73b099ca96d1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87284 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lib/bootmode: Enforce display init requirement for vbootSubrata Banik2025-04-121-3/+5
| | | | | | | | | | | | | | | | | | | | The `display_init_required` function for vboot now mandates that either `CONFIG_VBOOT_MUST_REQUEST_DISPLAY` or `CONFIG_VBOOT_ALWAYS_ENABLE_DISPLAY` must be enabled. If neither of these Kconfig options is set when `CONFIG_VBOOT` is enabled, the code will now trigger `dead_code()`. This enforces the requirement that display initialization is explicitly requested or always enabled when vboot is active, aligning with the intended usage of `VB2_CONTEXT_DISPLAY_INIT`. TEST=Able to build google/fatcat. Change-Id: I371c0533057fb088ea15a5da6bd76173cea525aa Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/qualcomm: Use runtime check for QUP wrapper 2 initSubrata Banik2025-04-123-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the initialization logic for the optional QUPv3 wrapper 2. Add a runtime check of the `QUP_WRAP2_BASE` macro's value within `qupv3_fw_init`. This approach simplifies the QUP wrapper 2 initialization, making the code flow depend directly on whether a valid base address is defined for the target SoC. To facilitate this, explicitly define `QUP_WRAP2_BASE` as 0 (acting as a dummy entry) for SoCs like sc7180 and sc7280 which do not include this hardware block. The `if (QUP_WRAP2_BASE)` check will correctly evaluate to false for these platforms, skipping the initialization. Platforms that do have QUP wrapper 2 should define its non-zero base address. TEST=Able to build google/herobine. Change-Id: I553ee4891abc5dd744b69bcbee1cca2efd993ef3 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* soc/intel/common/cse: Skip CSE state setting with LITE_SYNC_BY_PAYLOADSubrata Banik2025-04-121-0/+3
| | | | | | | | | | | | | | | This commit introduces a conditional bypass for ME state setting, potentially reducing CBFS traversal time when searching for the `option/me_state` file. TEST=Able to build and boot google/fatcat. Change-Id: I43f5daab450989307d9b3529949e9f03cba4404d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87266 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/pantherlake: Increase heap size for high-quality FW splashSubrata Banik2025-04-121-0/+4
| | | | | | | | | | | | | | | | | | This patch increases the default heap size from 1MB to 2MB (0x200000) to accommodate rendering high-quality firmware splash BMP logos. The previous 1MB heap size might be insufficient for larger, more detailed OEM logos, potentially leading to memory exhaustion during the splash screen display. TEST=Able to render an OEM logo size ~512KB w/o any corruption. Change-Id: I850247befc3904b6dc52e9872e8b99d53c2c9564 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87265 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso/chipset.cb: Enable gpp_bridge_[a/b] by defaultMaximilian Brune2025-04-113-2/+4
| | | | | | | | | | | | | | | | | | Since FSP doesn't support disabling bridges and has no UPDs for that, they must be enabled in DT to make sure they are properly initialized during PCI enumeration as expected by the payload (EDK2 for example). It might be OK to have them set to off when all devices behind the bridge are also off and FSP disables those secondary devices. In general something that cannot be hidden/shut off shouldn't be marked as such, as later stages (payload/OS) might find it active, but unconfigured. Change-Id: I4104a6af00304b0a7c50ba0e09ad19a0ed9d2733 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86598 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne/chipset.cb: Enable gpp_bridge_[a/b/c] by defaultMaximilian Brune2025-04-112-3/+5
| | | | | | | | | | | | | | | | | | | Since FSP doesn't support disabling bridges and has no UPDs for that, they must be enabled in DT to make sure they are properly initialized during PCI enumeration as expected by the payload (EDK2 for example). It might be OK to have them set to off when all devices behind the bridge are also off and FSP disables those secondary devices. In general something that cannot be hidden/shut off shouldn't be marked as such, as later stages (payload/OS) might find it active, but unconfigured. Change-Id: Ie34bb2abc0211963b2613d1b50b1767df31c1062 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* src/soc/amd/* : Move CPU init in common codeNaresh Solanki2025-04-118-66/+20
| | | | | | | | | | | | | | AMD SoC from family 17h share common cpu init code. Move those to common/block/cpu/noncar/cpu.c TEST=Build for glinda SoC & check for boot. Change-Id: If53455f359302f368f7c979defa2c1088c5c2f16 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* util/mtkheader: Rename to util/mediatekYu-Ping Wu2025-04-118-8/+8
| | | | | | | | | | | | To allow adding more scripts to the util/mtkheader folder, rename it to util/mediatek. Also update description.md and regenerate Documentation/util.md and util/README.md by util_readme.sh. Change-Id: Ibc6ef9dddc541d2dd471898af431cadde231edca Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
generated by cgit v1.2.3 (git 2.46.0) at 2025-04-27 02:24:00 +0000