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* printf: Use inttype.h macros for format stringsThomas Heijligen2023-04-271-5/+5
| | | | | | | | | | | | | | DJGPP for compiling DOS has other sizes for the normal int types and therefore throwing errors when using %i %d or %x with uint32_t. Fix these warnings by using the macros created for it and provided in inttypes.h. Change-Id: Ia75b6df981ce60c891161fe553c7ceab8570178d Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73040 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25.c: Rename spi_get_erasefn_from_opcode to spi25_get_erasefn_from_opcodeThomas Heijligen2022-12-141-5/+5
| | | | | | | | | | | This function works only with spi25 chips Change-Id: Ie054160b0fdd34bcb128285c6a047e3a3fa8be0c Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67716 Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25.c: Move spi_get_opcode_from_erasefn() to spi.cThomas Heijligen2022-12-141-12/+0
| | | | | | | | | | | | Split spi_get_opcode_from_erasefn() out into spi.c to add support for non spi25 flashes next. Change-Id: Id654e998d0af2d3f5845336bb98b38d724519038 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67715 Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Convert flashchip erase_block func ptr to enumerateEdward O'Callaghan2022-11-111-4/+4
| | | | | | | | | | | | | | This forges the way for flashchips.c to be pure declarative data and lookup functions for dispatch to be pure. This means that the flashchips data could be extracted out to be agnostic data of the flashrom code and algorithms. Change-Id: I02ae7e4c67c5bf34ec2fd7ffe4af8a2aba6fd5e5 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69133 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Convert flashchips db to use indirection for erase_blockEdward O'Callaghan2022-11-111-16/+16
| | | | | | | | | | | | | | This paves the way to allow for the conversion of flashchip erase_block func ptr to enumerate values. This change should be a NOP. TEST=`diff -u <(objdump -D flashchips.o_bk) <(objdump -D flashchips.o)`. Change-Id: I122295ec9add0fe0efd27273c9725e5d64f6dbe2 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69131 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree: provide flashrom context into programmer_delay()Alexander Goncharov2022-10-171-1/+1
| | | | | | | | | | | | | | | | | Modify the `programmer_delay` function signature to allow passing the flashrom context. Programmers that depend on internal delay should provide NULL as a context. The use of this function parameter will be introduced in CB:67393. TOPIC=programmer_handle_global TEST=builds Change-Id: Ibb0bce26ce2052853ee52158d7ba742967a9e229 Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* spi25.c: Retype appropriate variables with boolFelix Singer2022-09-081-5/+5
| | | | | | | | | | | | Use the bool type instead of an integer for appropriate variables, since this represents their purpose much better. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: Icd7e6478848c6f72817da16a5350d450bcc0bb5d Reviewed-on: https://review.coreboot.org/c/flashrom/+/66890 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* spi25.c: Add function to return opcode of passed erase fucntion pointerAarya Chaumal2022-06-271-0/+12
| | | | | | | | | | | | | There is a function, spi_get_erasefn_from_opcode, which returns the erase function for given opcode. Add a function which does the opposite i.e. returns the opcode for given erase function. Change-Id: Ia3aefc9b9465efdd16b1678bb2ada9a23f00d316 Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Thomas Heijligen <src@posteo.de>
* spi25.c: Add a list to lookup erasefn and opcode instead of switch caseAarya Chaumal2022-06-271-39/+28
| | | | | | | | | | | | | Add a list (erasefn, opcode) which maps opcodes to erase functions. Modify the spi_get_opcode_from_erasefn to use this list. Change-Id: I126f88c313ad309b509b367f9087235b87df6136 Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Simon Buhrow Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashchips,spi25: Replace `.wrea_override` with FEATURE_4BA_EAR_1716Nico Huber2022-06-231-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | There are two competing sets of instructions to access the extended address register of 4BA SPI chips. Some chips even support both sets. So far, we assumed the 0xc5/0xc8 instructions by default and allowed to override the write instructions with the `.wrea_override` field. This has some disadvantages: * The additional field is easily overlooked. So when adding a new flash chip, one might assume only 0xc5/0xc8 are supported. * We cannot describe flash chips completely that allow both instructions (and some programmers may be picky about which instructions can be used). Therefore, replace the `.wrea_override` field with a feature flag. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: I6d82f24898acd0789203516a7456fd785907bc10 Ticket: https://ticket.coreboot.org/issues/357 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashchips: Rename FEATURE_4BA_EXT_ADDR -> _EAR_C5C8Nico Huber2022-06-221-1/+1
| | | | | | | | | | | | | | There are two competing sets of instructions to access the extended address register of 4BA SPI chips. Some chips even support both sets. To prepare for other instructions than the default 0xc5/0xc8, rename the original feature flag. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: Iacb7b68a9e3444fe28873ff0fe5e3fab16643c8c Ticket: https://ticket.coreboot.org/issues/357 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashchips: Add Spansion (today Infineon) S25FL128L and S25FL256LNico Huber2022-06-201-0/+9
| | | | | | | | | | | | | | | | | | | | | | | These chips seem to be rather regular, supporting 2.7V..3.6V, the common erase block sizes 4KiB, 32KiB, 64KiB and the usual block- protection bits. Status/configuration register naming differs from other vendors, though. These chips have 2 status registers plus 3 configuration registers. Configuration registers 1 & 2 match status registers 2 & 3 of what we are used from other vendors. Read opcodes match too, however writes are always done through the WRSR instruction which can write up to 4 bytes (SR1, CR1, CR2, CR3). S25FL256L supports native 4BA commands and entering a 4BA mode. However, it uses an unusual opcode (0x53) for the 32KiB 4BA block erase. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: I356df6649f29e50879a4da4183f1164a81cb0a09 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64747 Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* libflashrom: Return progress state to the library userRichard Hughes2022-05-251-0/+7
| | | | | | | | | | | | | | | | | | | | | | Projects using libflashrom like fwupd expect the user to wait for the operation to complete. To avoid the user thinking the process has "hung" or "got stuck" report back the progress complete of the erase, write and read operations. Add a new --progress flag to the CLI to report progress of operations. Include a test for the dummy spi25 device. TEST=./test_build.sh; ./flashrom -p lspcon_i2c_spi:bus=7 -r /dev/null --progress Change-Id: I7197572bb7f19e3bdb2bde855d70a0f50fd3854c Signed-off-by: Richard Hughes <richard@hughsie.com> Signed-off-by: Daniel Campello <campello@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/49643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* spi25_statusreg: delete spi_read_status_register()Nikolai Artemiev2022-04-051-4/+9
| | | | | | | | | | | | | | | | | | | | | | | Delete the spi_read_status_register() function because the generic spi_read_register() function can be used instead. This patch also converts all call sites over to spi_read_register(). A side effect is that error codes are now properly propagated and checked. BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom -{r,w,E} TEST=Tested with a W25Q128.W flash on a kasumi (AMD) dut. Read SR1/SR2 with --wp-status and activated various WP ranges that toggled bits in both SR1 and SR2. Change-Id: I146b4b5439872e66c5d33e156451a729d248c7da Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* spi25.c: Use JEDEC consts in spi_simple_write_cmd() callsEdward O'Callaghan2020-10-311-10/+10
| | | | | | | | | | | | | | | | | | | | | | Make use of the JEDEC_CE_{60,62,C7} defined constants of the op-codes in each of the spi_simple_write_cmd() calls to assist in readability. V.2: Squash in JEDEC_BE_{52,C4,D7,D8,50,81} && JEDEC_SE. Both 'S'ector and 'B'lock 'E'rasers now use the consts in spi.h. BUG=none BRANCH=none TEST=builds same object. Change-Id: I1876781672fe03302af4a6ff8d365f2e6c3b6f13 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47005 Reviewed-by: Shiyu Sun <sshiyu@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25.c: Use define const in spi_simple_write_cmd() fnEdward O'Callaghan2020-10-311-1/+1
| | | | | | | | | | | | | | | | This uses the JEDEC_WREN_OUTSIZE define in the spi_simple_write_cmd() helper function to improve readability. BUG=none BRANCH=none TEST=builds same object Change-Id: I1b5ede4435ba014320fa8cf9490dc23cdfba4fd6 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shiyu Sun <sshiyu@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* spi25.c: Replace tab with space after '=' symbolEdward O'Callaghan2020-10-171-1/+1
| | | | | | | | | | Trivial, only noticed while diff'ing with ChromiumOS fork. Change-Id: I247d9cb1910a9afdb0e7bfe81515d51514da6550 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/46481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* spi: Allow cached ID bytes to be clearedEdward O'Callaghan2020-08-261-34/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This does two things: 1. Removes the static variables from various ID functions and moves them to a single struct. 2. Adds a function to clear the struct. The idea of the original caching mechanism introduced years ago was simply to speed up probe_flash() by not issuing the same read ID commands dozens or hundreds of times for a single chip. That implementation assumed that we would only call probe_flash() once. However, there are cases when we want to call probe_flash() multiple times, for example, if using an external programmer and using different voltages (for probing the chip). This patch is extremely similar to the original works of: `commit 57b7524b1448189d3630d6c4735e60dbbdf14d51`. Author: David Hendricks <dhendrix@chromium.org> && `commit 7f7c711ee1a41649607f81f1533e5135fc1361fc`. Author: David Hendricks <dhendrix@chromium.org> BUG=b:15656443 BRANCH=none TEST=none Change-Id: I879cb08dbe66db9ab0c3b8a7f93b04fe1c5980f4 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* spi25.c: Factor out rdid_get_ids() and compare_id()Edward O'Callaghan2020-08-261-32/+30
| | | | | | | | | | | | | | | | | | This is in preparation for implementing a cache for the probe results of RDID and REMS (3&4-byte variant) commands. The intention is to make probing of SPI rom's slightly faster, a few 10's of ms dependant upon the spi master used. BUG=b:15656443 BRANCH=none TEST=builds Change-Id: I1556e97a7c70425069e3d1dc0d5daf0aeec4e7bf Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Revert "flashchips: port S25FS(128S) chip from chromiumos"Nico Huber2020-05-011-214/+4
| | | | | | | | | | | | | | | | | | | | | This reverts commit a3519561bd0fb44153bb376322b799000657576f. Breaks support for most SPI flash chips. It's too big and too invasive to be reviewed as a single commit. The changes to `spi_poll_wip():spi25.c` were not noticed in the original review that were from the similarly named function and file `s25f_poll_status():s25f.c` in the downstream Chromium fork. V.2: Rebase and rephrase commit msg to reflect how the issue slipped in. Change-Id: Id2a4593bdb654f8a26957d69d52189ce61621d93 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shiyu Sun <sshiyu@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* spi25.c: Add a null checkAngel Pons2020-04-251-0/+2
| | | | | | | | | Change-Id: I5fcc23d81b8404af90768afa2954509bf334ab2c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39974 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: port S25FS(128S) chip from chromiumossibradzic2020-04-221-4/+214
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This may seem too big just to support yet another flash chip, but in reality it brings support for whole new family of S25FS Spansion/Cypress flash chips. These chips require handling of some special status registers for erasing or writing, with very specific timing checks in place. For example, WIP status bit will remain being set to 1 if erase or programming errors occur, and in that case chip 'software reset' has to be performed otherwise the chip will remain unresponsive to all further commands. Also, special CR3NV register (Configuration Register 3 Nonvolatile) status bits needs to be read and set by using RDAR (ReaD Any Register) and WRAR (WRite Any Register) OP commands, and these states are needed to determine which type of reset feature is enabled at the time (legacy or S25FS type) in the first place, determine whether Uniform or Hybrid sector architecture is used at the time, or set programming buffer address wrap point (256 or 512 bytes). Furthermore, S25FS chip status register has to be restored to its original state (hence that ugly CHIP_RESTORE_CALLBACK) following erasing or writing, failing to do so may result in host being unable to access data on the chip at all. Finally, although this brings support for the whole family of chips, I only have one such chip to do the actual testing, S25FS128S (Small Sectors), which I had fully tested on ch341a and FT4232H programmers, with confirmed working probe, read, erase and write. Full summary of changes are here: flashchips: add new flashchip sctructure property: .reset add chip definitions: S25FS128S Large Sectors S25FS128S Small Sectors flash: add macro (chip_restore_func_data call-back): CHIP_RESTORE_CALLBACK flashrom: add struct: chip_restore_func_data add call-back function: register_chip_restore spi: add OP codes: CMD_RDAR, CMD_WRAR, CMD_WRAR_LEN, CMD_RSTEN, CMD_RST add register bit function definitions: CR3NV_ADDR, CR3NV_20H_NV add timers: T_W, T_RPH, T_SE spi25: refactor (based on chromiumos implementation) function: spi_poll_wip port these functions from chromiumos: probe_spi_big_spansion s25fs_software_reset s25f_legacy_software_reset s25fs_block_erase_d8 spi25_statusreg: port these functions from chromiumos: spi_restore_status s25fs_read_cr s25fs_write_cr s25fs_restore_cr3nv Most of the ported functions are originally from s25f.c found at https://chromium.googlesource.com/chromiumos/third_party/flashrom with exception of spi_restore_status which is defined in spi25_statusreg.c. The rest of macros and OP codes are defined in same files as in this commit. Change-Id: If659290874a4b9db6e71256bdef382d31b288e72 Signed-off-by: Samir Ibradzic <sibradzic@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* spi25: Remove dead incrementElyes HAOUAS2019-07-191-1/+0
| | | | | | | | | | | Value stored in 'pos' is never read. Found-by: scan-build 7.0.1-8 Change-Id: I9a70593f182d7558e71e831fc2b834ac58a25b2a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34404 Tested-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
* spi25: Fix layering violation in probe_spi_rdid4()Nico Huber2019-06-271-20/+5
| | | | | | | | | | | | Move the message to a lower level where we can do a more generic check and don't need internal knowledge of the SPI-master driver. Change-Id: Idd21d20465cb214f3ff5bf3267b9014f8beee3f3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* tree: Make internal functions staticJacob Garber2019-06-231-3/+3
| | | | | | | | | | | | None of these functions are used outside of the files they are defined in, so make them all static. Change-Id: Ie9cbe12d289bcedacf2f1bf483ae64ef8039ccc1 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
* spi25: Fix layering violation in default_spi_write_aai()Nico Huber2019-06-211-14/+0
| | | | | | | | Change-Id: I8aa3e2992f64906edc669060936f9522d32637fb Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* spi: Move 16MiB partitioning up into spi_chip_read()Nico Huber2019-06-211-32/+9
| | | | | | | | | | | | | We enforced a 16MiB limit in spi_read_chunked() for multi-die flash chips that can't be fully read at once. The same limit can be useful for dediprog programmers. So move it into a more generic place. Change-Id: Iab1fd5b2ea550b4b3ef3e8402e0b6ca218485a51 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33613 Reviewed-by: Ryan O'Leary Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* dediprog: Implement 4BA EAR mode for protocol v1Nico Huber2019-06-041-1/+1
| | | | | | | | | | | | | | With an SF100 and protocol version 1, using the extended address register of the flash chip seems safe. Make use of that and remove the broken 4BA modes flag. Tested with SF100 V:5.1.9 and W25Q256FV. Change-Id: If926cf3cbbebf88231116c4d65bafc19d23646f6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/32016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* Fix several -Wno-missing-field-initializers warningsRichard Hughes2019-02-031-0/+6
| | | | | | | | Change-Id: Ib4487d4c1a38fa8471fa1f9034604412e9d14cf7 Signed-off-by: Richard Hughes <richard@hughsie.com> Reviewed-on: https://review.coreboot.org/c/30405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Enable 4BA mode for Spansion 25FL256SNico Huber2018-10-031-0/+2
| | | | | | | | | | | 4BA mode is entered by setting bit 7 for the extended address register. Change-Id: I807bf55d65763a9f48a6a3377f14f4e5288a7a4c Signed-off-by: Nico Huber <nico.h@gmx.de> Tested-by: Michael Fuckner <michael@fuckner.net> Reviewed-on: https://review.coreboot.org/25133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* flashchips: Add Spansion 25FL256S......0Nico Huber2018-10-031-1/+2
| | | | | | | | | | | | | | | | The Spansion 25SFL256S supports 4BA through an extended address register, a 4BA mode set by bit 7 of that register, or native 4BA instructions. Enable the former only for now. Unfortunately the S25SF256S uses another instruction to write the exten- ded address register. So we add an override for the instruction byte. Change-Id: I0a95a81dfe86434f049215ebd8477392391b9efc Signed-off-by: Nico Huber <nico.h@gmx.de> Tested-by: Michael Fuckner <michael@fuckner.net> Reviewed-on: https://review.coreboot.org/25132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* Remove address from GPLv2 headersElyes HAOUAS2018-04-241-4/+0
| | | | | | | | Change-Id: I7bfc339673cbf5ee2d2ff7564c4db04ca088d0a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* spi25: Revise decision when to enter/exit 4BA modeNico Huber2018-01-021-27/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of arbitrarily deciding whether to enter 4BA mode in the flash chip's declaration, advertise that entering 4BA mode is supported and only enter it if the SPI master supports 4-byte addresses. If not, exit 4BA mode (the chip might be in 4BA mode after reset). If we can't assure the state of 4BA mode, we bail out to simplify the code (we'd have to ensure that we don't run any instructions that can usually be switched to 4BA mode otherwise). Two new feature flags are introduced: * FEATURE_4BA_ENTER: Can enter/exit 4BA mode with instructions 0xb7/0xe9 w/o WREN. * FEATURE_4BA_ENTER_WREN Can enter/exit 4BA mode with instructions 0xb7/0xe9 after WREN. FEATURE_4BA_SUPPORT is dropped, it's completely implicit now. Also, draw the with/without WREN distinction into the enter/exit functions to reduce code redundancy. Change-Id: I877fe817f801fc54bd0ee2ce4e3ead324cbb3673 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22422 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* spi_master: Introduce SPI_MASTER_4BA feature flagNico Huber2018-01-021-5/+10
| | | | | | | | | | | | | | | Add a feature flag SPI_MASTER_4BA to `struct spi_master` that advertises programmer-side support for 4-byte addresses in generic commands (and read/write commands if the master uses the default implementations). Set it for all masters that handle commands address-agnostic. Don't prefer native 4BA instructions if the master doesn't support them. Change-Id: Ife66e3fc49b9716f9c99cad957095b528135ec2c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* spi: Move ICH BBAR quirk out of the wayNico Huber2017-12-281-23/+3
| | | | | | | | | | | | | | | | | | | | | Get rid of the layering violations around ICH's BBAR. Move all the weird address handling into (surprise, surprise) `ichspi.c`. Might fix writes for the `BBAR != 0` case by accident. Background: Some ICHs have a BBAR (BIOS Base Address Configuration Register) that, if set, limits the valid address range to [BBAR, 2^24). Current code lifted addresses for REMS, RES and READ operations by BBAR, now we do it for all addresses in ichspi. Special care has to be taken if the BBAR is not aligned by the flash chip's size. In this case, the lower part of the chip (from BBAR aligned down, up to BBAR) is inacces- sible (this seems to be the original intend behind BBAR) and has to be left out in the address offset calculation. Change-Id: Icbac513c5339e8aff624870252133284ef85ab73 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22396 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25: Merge remainder of spi4ba inNico Huber2017-12-281-1/+86
| | | | | | | | Change-Id: If581e24347e45cbb27002ea99ffd70e334c110cf Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22388 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25: Remove now obsolete `four_bytes_addr_funcs` pathNico Huber2017-12-281-23/+7
| | | | | | | | Change-Id: Idb7c576cb159630da2268813388b497cb5f46b43 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22386 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25: Enable native 4BA read and write using feature bitsNico Huber2017-12-281-18/+23
| | | | | | | | | | | Prefer the native 4BA instruction when they are supported. In this case, override our logic to decide to use a 4BA address. Change-Id: I2f6817ca198bf923671a7aa67e956e5477d71848 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22385 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25: Integrate 4BA supportNico Huber2017-12-281-5/+28
| | | | | | | | | | | | | | | | | | Allow 4-byte addresses for instructions usually used with 3-byte addresses. Decide in which way the 4th byte will be communicated based on the state of the chip (i.e. have we enabled 4BA mode) and a new feature bit for an extended address register. If we are not in 4BA mode and no extended address register is available or the write to it fails, bail out. We cache the state of 4BA mode and the extended address register in the flashctx. Change-Id: I644600beaab9a571b97b67f7516abe571d3460c1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22384 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25: Use common code for nbyte read/write and block eraseNico Huber2017-12-281-427/+103
| | | | | | | | | | | | | | | | | | Introduce spi_prepare_address() and spi_write_cmd() and use them in nbyte_program, nbyte_read and block-erase procedures. The former abstracts over the address part of a SPI command to make it exten- sible for 4-byte adressing. spi_write_cmd() implements a WREN + write operation with address and optionally up to 256 bytes of data. It provides a common path to reduce overall redundancy. Also, reduce the polling delay in spi_block_erase_c4() from 500s to 500ms as the comment suggests. Change-Id: Ibc1ae48acbfbd427a30bcd64bdc080dc3dc20503 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* spi25: Introduce spi_simple_write_cmd()Nico Huber2017-12-281-95/+38
| | | | | | | | | | | | spi_simple_write_cmd() executes WREN plus a single byte write and polls WIP afterwards. It's used to replace current spi_erase_chip_*() imple- mentations. Change-Id: Ib244356fa471e15863b52e6037899d19113cb4a9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* 4BA: Flashrom integration for the 4-bytes addressing extensionsBoris Baykov2017-10-151-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch integrates code of the previous patch into Flashrom's code. All the integrations is around 3 functions spi_nbyte_read, spi_nbyte_program and spi_byte_program. After this patch then are not static and can be called by their pointers saved in flashchips array. Also I added to flashrom.c some code to switch a chip to 4-bytes addressing mode. And one error message is corrected in spi.c because it's not suitable for 32-bit addresses. Patched files ------------- flash.h + added set of 4-bytes address functions to flashchip structure definition flashrom.c + added switch to 4-bytes addressing more for chips which support it serprog.c + added 4-bytes addressing spi_nbyte_read call to serprog_spi_read spi.c + fixed flash chip size check in spi_chip_read spi25.c + added 4-bytes addressing spi_nbyte_read call to spi_read_chunked + added 4-bytes addressing spi_nbyte_program call to spi_write_chunked + added 4-bytes addressing spi_byte_program call to spi_chip_write_1 Conflicts: serprog.c Change-Id: Ib051cfc93bd4aa7580519e0e6206d025f3ca8049 Signed-off-by: Boris Baykov <dev@borisbaykov.com>, Russia, Jan 2014 [clg: ported from https://www.flashrom.org/pipermail/flashrom/2015-January/013205.html ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-on: https://review.coreboot.org/20505 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Enable continuous SPI readsUrja Rannikko2017-07-131-13/+14
| | | | | | | | | | | | | Previous unnecessary page-by-page reading is repurposed to read by big naturally aligned areas (now chip size limited to 16MB for future-proofing of 4 byte addressed multi-die chips) and serprog hack for continuous reads is removed. Change-Id: Iadf909c9216578b1c5dacd4c4991bb436e32edc9 Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-on: https://review.coreboot.org/20223 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25: ignore 0x00 as a manufacturer id in the generic matchUrja Rannikko2015-06-221-2/+2
| | | | | | | | | | | | | | Saying that manufacturer id 0x00 is an "unknown SPI chip" just confuses people with external programmers without a proper connection to a chip and makes them think flashrom doesn't support the chip they're trying to use. Also causes unnecessary -c requirement with a multiple-slot (FWH/LPC and SPI) serprog device i was testing. Corresponding to flashrom svn r1893. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Rename programmer registration functionsCarl-Daniel Hailfinger2014-07-191-2/+2
| | | | | | | | | | | | Register_programmer suggests that we register a programmer. However, that function registers a master for a given bus type, and a programmer may support multiple masters (e.g. SPI, FWH). Rename a few other functions to be more consistent. Corresponding to flashrom svn r1831. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add 'const' keyword to chip write and other function prototypesMark Marshall2014-05-091-6/+4
| | | | | | | | | | Corresponding to flashrom svn r1789. Inspired by and mostly based on a patch Signed-off-by: Mark Marshall <mark.marshall@omicron.at> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Report if we are not able to disable AAI mode againStefan Tauner2014-04-261-5/+9
| | | | | | | Corresponding to flashrom svn r1780. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* CID1130000: Unchecked return value in default_spi_write_aai()Stefan Reinauer2014-04-261-9/+12
| | | | | | | | | | | Also, try to always disable WRDI because else the user is stuck with a chip in AAI mode that won't return by itself w/o a reset. Corresponding to flashrom svn r1779. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for remaining Numonyx (Micron) N25Q chipsNikolay Nikolaev2013-06-281-0/+45
| | | | | | | | | | | | | | | | | | | | Add... - N25Q128..3E - N25Q128..1E - N25Q256..1E (defunct due to addressing) - N25Q256..3E (defunct due to addressing) - N25Q512..1E (defunct due to addressing) - N25Q512..3E (defunct due to addressing) - N25Q00A..3G (defunct due to addressing) Also, refine existing family members. Corresponding to flashrom svn r1693. Signed-off-by: Nikolay Nikolaev <evrinoma@gmail.com> Reviewed-by: Steven Zakulec <spzakulec@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Introduce spi_block_erase_db()Nikolay Nikolaev2013-06-281-0/+43
| | | | | | | | | | | | Used for page erase on some chips (e.g. Numonyx M45PE and Sanyo LF25FW series). Corresponding to flashrom svn r1682. Signed-off-by: Nikolay Nikolaev <evrinoma@gmail.com> Reviewed-by: Steven Zakulec <spzakulec@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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