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| * clk: renesas: r8a77980: Add I2C5 clockNikita Yushchenko2023-03-301-0/+1
| | | | | | | | | | | | | | | | | | The MSSR clock definition for I2C5 was missing. Add it. Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230328033902.830269-1-nikita.yoush@cogentembedded.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: Convert to platform remove callback returning voidUwe Kleine-König2023-03-161-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230312161512.2715500-24-u.kleine-koenig@pengutronix.de Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r9a06g032: Improve clock tablesRalph Siemsen2023-03-101-153/+407
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Each entry in the clock table specifies a number of individual bits in registers, for contolling clock reset, gaiting, etc. These reg/bit were packed into a u16 to save space. The combined value is difficult to understand when reviewing the clock table entries. Introduce a "struct regbit" which still occupies only 16 bits, but allows the register and bit values to be specified explicitly. Convert all previous uses of u16 for reg/bit into "struct regbit". The bulk of this patch converts the clock table to use struct regbit, making use of the RB() helper macro. The conversion was automated by script, and as a further verification, the compiled binary of the table was compared before/after the change (with objdump -D). The clk_rdesc_set() function now checks for zero reg/bit internally. This allows callers of that function to remove those checks. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230301215520.828455-5-ralph.siemsen@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r9a06g032: Document structsRalph Siemsen2023-03-101-1/+49
| | | | | | | | | | | | | | | | | | | | Add some kerneldoc comments for the structures. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230301215520.828455-4-ralph.siemsen@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r9a06g032: Drop unused fieldsRalph Siemsen2023-03-101-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Drop three unused fields from the clock descriptor structure, and update the macros for filling such structures accordingly. The values for such fields are kept in the source code, now unused, in case they are needed later. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230301215520.828455-3-ralph.siemsen@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r9a06g032: Improve readabilityRalph Siemsen2023-03-101-41/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several small readability improvements: - Move enum gate_type definition up and add comments to each field. - Use this enum instead of generic uint32_t type in clock desc struct. - Tidy up bitfield syntax and comments in clock desc structure - Reformat macros for building clock desc to have one assignment per line There is no functional change. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230301215520.828455-2-ralph.siemsen@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a77980: Add Z2 clockGeert Uytterhoeven2023-03-101-0/+1
| | | | | | | | | | | | | | | | Add support for the Z2 (Cortex-A53 System CPU) clock on R-Car V3H, which uses a fixed SYS-CPU divider. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/aad9eaa57acf65cbe43e4d374066a72d760d54d8.1676560357.git.geert+renesas@glider.be
| * clk: renesas: r8a77970: Add Z2 clockGeert Uytterhoeven2023-03-101-0/+1
| | | | | | | | | | | | | | | | Add support for the Z2 (Cortex-A53 System CPU) clock on R-Car V3M, which uses a fixed SYS-CPU divider. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/6a9169e5bc92c2b9549292769a0814e04b9147cf.1676560357.git.geert+renesas@glider.be
| * clk: renesas: r8a77995: Fix VIN parent clockGeert Uytterhoeven2023-03-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | According to the R-Car Series, 3rd Generation Hardware User’s Manual Rev. 2.30, the parent clock of the Video Input Module (VIN) on R-Car D3 is S3D1. Update the driver to match the documentation. This has no functional impact, as both S1D2 and S3D1 have the same clock rate, and are always-on clocks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/9b655843a260e06fa6f3349cdafac180e2bf38a5.1676368776.git.geert+renesas@glider.be
| * clk: renesas: r8a77980: Add VIN clocksNiklas Söderlund2023-03-061-0/+16
| | | | | | | | | | | | | | | | | | | | Add the VIN module clocks, which are used by the VIN modules on the Renesas R-Car V3H (R8A77980) SoC. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230211153026.3898491-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a779g0: Add VIN clocksNiklas Söderlund2023-03-061-0/+16
| | | | | | | | | | | | | | | | | | | | Add the VIN module clocks, which are used by the VIN modules on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230211143655.3809756-4-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a779g0: Add ISPCS clocksNiklas Söderlund2023-03-061-0/+2
| | | | | | | | | | | | | | | | | | | | Add the ISPCS0 and ISPCS1 module clocks, which are used by the ISPCS modules on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230211143655.3809756-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a779g0: Add CSI-2 clocksNiklas Söderlund2023-03-061-0/+3
| | | | | | | | | | | | | | | | | | | | Add the CSI core clock and the CSI40 and CSI41 module clocks, which are used by the CSI-2 Interfaces on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230211143655.3809756-2-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a779g0: Add thermal clockGeert Uytterhoeven2023-03-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add the module clock used by the Thermal Sensor/Chip Internal Voltage Monitor/Core Voltage Monitor (THS/CIVM/CVM) on the Renesas R-Car V4H (R8A779G0) SoC. Based on a large patch in the BSP by Kazuya Mizuguchi. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/59461effd0d9f7a39e0c91352c87f2b7071b1891.1675958536.git.geert+renesas@glider.be
| * clk: renesas: r8a779g0: Add Audio clocksKuninori Morimoto2023-03-061-0/+2
| | | | | | | | | | | | | | | | | | | | Add module clocks for the Audio (SSI/SSIU) blocks on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/878rhganfo.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: cpg-mssr: Update MSSR register range for R-Car V4HTakeshi Kihara2023-03-061-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | The SRCR, SRSTCLR, MSTPCR and MSTPSR registers for R-Car V4H (R8A779G0) each have registers up to offset 0x74. Update the corresponding arrays. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/87a61wanfx.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: remove MODULE_LICENSE in non-modulesNick Alcock2023-04-132-2/+0
|/ | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 8b41fc4454e ("kbuild: create modules.builtin without Makefile.modbuiltin or tristate.conf"), MODULE_LICENSE declarations are used to identify modules. As a consequence, uses of the macro in non-modules will cause modprobe to misidentify their containing object file as a module when it is not (false positives), and modprobe might succeed rather than failing with a suitable error message. So remove it in the files in this commit, none of which can be built as modules. Signed-off-by: Nick Alcock <nick.alcock@oracle.com> Suggested-by: Luis Chamberlain <mcgrof@kernel.org> Cc: Luis Chamberlain <mcgrof@kernel.org> Cc: linux-modules@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Hitomi Hasegawa <hasegawa-hitomi@fujitsu.com> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: linux-renesas-soc@vger.kernel.org Cc: linux-clk@vger.kernel.org Signed-off-by: Luis Chamberlain <mcgrof@kernel.org>
* clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*Wolfram Sang2023-02-105-173/+13
| | | | | | | | | | | | | | | | R-Car H3 ES1.* was only available to an internal development group and needed a lot of quirks and workarounds. These become a maintenance burden now, so our development group decided to remove upstream support for this SoC. Public users only have ES2 onwards. In addition to the ES1 specific removals, a check for it was added preventing the machine to boot further. It may otherwise inherit wrong clock settings from ES2 which could damage the hardware. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230202092332.2504-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a779g0: Add CAN-FD clocksGeert Uytterhoeven2023-01-261-0/+2
| | | | | | | | Add the CANFD core clock and the CANFD0 module clock, which are used by the CAN-FD Interface on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/a78f534bd80f170f3f1267f3270fdb3b7a73b5d4.1674498643.git.geert+renesas@glider.be
* clk: renesas: r8a779g0: Tidy up DMAC name on SYS-DMACKuninori Morimoto2023-01-261-2/+2
| | | | | | | | | "sydm" is a bit name. Let's rename it to the common "sys-dmac". Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/87v8l3z3y8.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a779a0: Tidy up DMAC name on SYS-DMACKuninori Morimoto2023-01-261-2/+2
| | | | | | | | | "sydm" is a bit name. Let's rename it to the common "sys-dmac". Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/87tu0nz3xr.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a779g0: Add custom clock for PLL2Geert Uytterhoeven2023-01-243-7/+164
| | | | | | | | | | | | | | | | | | | | Currently the PLLs are modeled as fixed factor clocks, based on initial settings. However, enabling CPU boost clock rates requires increasing the PLL clock rates. Add a custom clock driver to model the PLL clocks on R-Car Gen4, and use it for PLL2 on R-Car V4H. This allows the Z clock (Cortex-A76 core clock) to request PLL rate changes, and enable boost mode for the High Performance mode. For now this is limited to integer multiplication modes. Note that the definition for CPG_PLLxCR0_NI uses the value for R-Car V4H. On R-Car S4-8, the integer and fractional multiplication fields are one bit larger resp. smaller, but R-Car S4-8 does not support High Performance mode. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/76a5952900a6e15604c640bc8a27762e0e936677.1670492384.git.geert+renesas@glider.be
* clk: renesas: cpg-mssr: Remove superfluous check in resume codeGeert Uytterhoeven2023-01-231-3/+2
| | | | | | | | | | When the code flow arrives at printing the error message in cpg_mssr_resume_noirq(), we know for sure that we are not running on an RZ/A Soc, as the code checked for that before. Fixes: ace342097768e35f ("clk: renesas: cpg-mssr: Fix STBCR suspend/resume handling") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/144a3e66d748c0c17f3524ac8fa6ece5bf5b6f1e.1673425314.git.geert+renesas@glider.be
* clk: renesas: r9a06g032: Handle h2mode setting based on USBF presenceHerve Codina2023-01-231-0/+28
| | | | | | | | | | | | | | | | The CFG_USB[H2MODE] allows to switch the USB configuration. The configuration supported are: - One host and one device or - Two hosts Set CFG_USB[H2MODE] based on the USBF controller (USB device) availability. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230105152257.310642-3-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: cpg-mssr: Fix use after free if cpg_mssr_common_init() failedAlexey Khoroshilov2023-01-121-1/+2
| | | | | | | | | | | | | | If cpg_mssr_common_init() fails after assigning priv to global variable cpg_mssr_priv, it deallocates priv, but cpg_mssr_priv keeps dangling pointer that potentially can be used later. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 1f7db7bbf031 ("clk: renesas: cpg-mssr: Add early clock support") Signed-off-by: Alexey Khoroshilov <khoroshilov@ispras.ru> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/1671806417-32623-1-git-send-email-khoroshilov@ispras.ru Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r9a07g044: Add clock and reset entries for CRULad Prabhakar2023-01-121-1/+25
| | | | | | | | | | | | | | Add CRU clock and reset entries to CPG driver. CRU_SYSCLK and CRU_VCLK clocks need to be turned ON/OFF in particular sequence for the CRU block hence add these clocks to r9a07g044_no_pm_mod_clks[] array and pass it as part of CPG data for both RZ/G2L and RZ/V2L SoCs. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20221221212703.348278-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entriesPhil Edworthy2022-12-271-0/+20
| | | | | | | | | Add SDHI/eMMC clock/reset entries to CPG driver. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20221213230129.549968-2-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r9a09g011: Add USB clock and reset entriesBiju Das2022-12-271-0/+21
| | | | | | | | | Add USB clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20221212172804.1277751-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r9a09g011: Add TIM clock and reset entriesBiju Das2022-12-271-0/+22
| | | | | | | | | | | | | | | | | Add Compare-Match Timer (TIM) clock and reset entries to CPG driver. The TIM IP on the RZ/V2M comes with 32 channels, but the ISP has full control of channels 0 to 7, and channels 24 to 31. Therefore Linux is only allowed to use channels 8 to 23. The TIM has shared peripheral clock with other modules, so mark it as critical clock. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20221205145955.391526-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a779g0: Add display related clocksTomi Valkeinen2022-12-261-0/+9
| | | | | | | | | | | | | | Add clocks related to display which are needed to get the DSI output working. Extracted from Renesas BSP tree. Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20221201095631.89448-4-tomi.valkeinen+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: rcar-gen4: Restore PLL enum sort orderGeert Uytterhoeven2022-12-261-1/+1
| | | | | | | | | | When CLK_TYPE_GEN4_PLL4 was added to the rcar_gen4_clk_types enum, it was inserted at a random location. Restore sort order of the clock types referring to PLLs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/dbd61ed19f79e9ae751fbb533d6c946e810e4359.1669740824.git.geert+renesas@glider.be
* clk: renesas: r8a779g0: Fix OSC predividersGeert Uytterhoeven2022-12-261-4/+4
| | | | | | | | | | | | According to the table in Note 5 for the OSC clock in Table 8.1.4e ("Lists of CPG clocks generated from PLL5") of the R-Car V4H Series Hardware User's Manual Rev. 0.54, the predividers for the OSC clock are 16 resp. 32 when using a 16.66 resp. 33.33 MHz external crystal. Fixes: 0ab55cf1834177a2 ("clk: renesas: cpg-mssr: Add support for R-Car V4H") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/dcd572acc584c237f70d2309e038f25040236a87.1669740722.git.geert+renesas@glider.be
* clk: renesas: r9a09g011: Add PWM clock and reset entriesBiju Das2022-12-261-0/+10
| | | | | | | | | | | | | | | | | | | Add PWM{8..14} clock and reset entries to CPG driver. The PWM IP on the RZ/V2M comes with 16 channels, but the ISP has full control of channels 0 to 7, and channel 15, therefore Linux is only allowed to use channels 8 to 14. The PWM channel 15 shares apb clock and reset with PWM{8..14}. The reset is deasserted by the bootloader/ISP. Add PWM{8..14} clocks to CPG driver and mark apb clock as critical clock, so that the apb clock will be always on. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20221124191643.3193423-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a779f0: Fix Ethernet Switch clocksGeert Uytterhoeven2022-11-161-2/+2
| | | | | | | | | | | The RSwitch2 and EtherTSN-IF clocks were accidentally mixed up. While at it, rename them to better match the (future) documentation. Fixes: a3b4137a4d4023e6 ("clk: renesas: r8a779f0: Add Ethernet Switch clocks") Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/99b8b41bd2c5043c9e457862ef4bc144869eca58.1668501212.git.geert+renesas@glider.be
* clk: renesas: r8a779g0: Add Z0 clock supportGeert Uytterhoeven2022-11-151-0/+1
| | | | | | | | | | Add support for the Z0 (Cortex-A76 Sub-System) clock on R-Car V4H, based on the existing support for Z clocks on R-Car Gen4. Extracted from a patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/75daa1fd8fa7eaef7b8945bb5906c787222c7ac4.1668423063.git.geert+renesas@glider.be
* clk: renesas: r8a779g0: Add CMT clocksWolfram Sang2022-11-081-0/+4
| | | | | | Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20221104151135.4706-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a779g0: Add TMU and SASYNCRT clocksWolfram Sang2022-11-081-0/+6
| | | | | | Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20221103205546.24836-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a779f0: Fix SCIF parent clocksWolfram Sang2022-11-081-4/+4
| | | | | | | | | | | | | | | | As serial communication requires a clean clock signal, the Serial Communication Interfaces with FIFO (SCIF) are clocked by a clock that is not affected by Spread Spectrum or Fractional Multiplication. Hence change the parent clocks for the SCIF modules from the S0D12_PER clock to the SASYNCPERD4 clock (which has the same clock rate), cfr. R-Car S4-8 Hardware User's Manual rev. 0.81. Fixes: 24aaff6a6ce4 ("clk: renesas: cpg-mssr: Add support for R-Car S4-8") Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20221103143440.46449-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a779f0: Fix HSCIF parent clocksWolfram Sang2022-11-081-4/+4
| | | | | | | | | | | | | | | | As serial communication requires a clean clock signal, the High Speed Serial Communication Interfaces with FIFO (HSCIF) are clocked by a clock that is not affected by Spread Spectrum or Fractional Multiplication. Hence change the parent clocks for the HSCIF modules from the S0D3_PER clock to the SASYNCPERD1 clock (which has the same clock rate), cfr. R-Car S4-8 Hardware User's Manual rev. 0.81. Fixes: 080bcd8d5997 ("clk: renesas: r8a779f0: Add HSCIF clocks") Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20221103143440.46449-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r9a06g032: Repair grave increment errorMarek Vasut2022-11-011-2/+1
| | | | | | | | | | | | If condition (clkspec.np != pd->dev.of_node) is true, then the driver ends up in an endless loop, forever, locking up the machine. Fixes: aad03a66f902 ("clk: renesas: r9a06g032: Add clock domain support") Reviewed-by: Ralph Siemsen <ralph.siemsen@linaro.org> Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Gareth Williams <gareth.williams.jx@renesas.com> Link: https://lore.kernel.org/r/20221028113834.7496-1-marex@denx.de Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: rzg2l: Don't assume all CPG_MOD clocks support PMLad Prabhakar2022-10-282-15/+28
| | | | | | | | | | | | | | | | | | | There are cases where not all CPG_MOD clocks should be assumed to support PM. For example on the CRU block there is a particular sequence that needs to be followed to initialize the CSI-2 D-PHY in which individual clocks need to be turned ON/OFF, due to which Runtime PM support wasn't used by the CRU CSI-2 driver. This patch adds support to allow indicating if PM is not supported by the CPG_MOD clocks. Two new members no_pm_mod_clks and num_no_pm_mod_clks are added to struct rzg2l_cpg_info so that MOD clocks which do not support PM can be passed by no_pm_mod_clks[] array and when the driver uses Runtime PM support the clk ID is matched against the no_pm_mod_clks[] array to see if the clk is needed to be included as part of Runtime PM. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20221026014227.162121-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: rzg2l: Fix typo in struct rzg2l_cpg_priv kerneldocLad Prabhakar2022-10-261-1/+1
| | | | | | | | | | | | Fix typo pll5_mux_dsi_div_params -> mux_dsi_div_params Fixes the below warning (make W=1): drivers/clk/renesas/rzg2l-cpg.c:115: warning: Function parameter or member 'mux_dsi_div_params' not described in 'rzg2l_cpg_priv' Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20221026012123.159790-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a779a0: Fix SD0H clock nameWolfram Sang2022-10-261-1/+1
| | | | | | | | | | Correct the misspelled textual name of the SD0H clock. Fixes: 470e3f0d0b15 ("clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver") Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20221012184830.3199-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a779g0: Add RPC-IF clockGeert Uytterhoeven2022-10-261-1/+2
| | | | | | | | | | | | Add the module clock used by the SPI Multi I/O Bus Controller (RPC-IF) on the Renesas R-Car V4H (R8A779G0) SoC. While at it, fix table alignment in the definition of the related RPCSRC internal clock. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/f0609c82e742865be753b67a0a6080f193f405ad.1665583328.git.geert+renesas@glider.be
* clk: renesas: r8a779g0: Add SDHI clocksGeert Uytterhoeven2022-10-261-1/+3
| | | | | | | | | Add the SD0H core clock and the SDHI module clock, which are used by the SD Card/MMC Interface on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/e9b05d102160cc3f7395ac53a533e81c07307d5e.1665558175.git.geert+renesas@glider.be
* clk: renesas: r8a779f0: Add SASYNCPER internal clockGeert Uytterhoeven2022-10-261-3/+5
| | | | | | | | | | | Add the SASYNCPER internal clock, which is the clock source of the various SASYNCPERD[124] clocks, to match the clock tree diagram in the documentation. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reported-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/18e6765bfc3bf7c3ee5ce93a370d377c1d17728e.1665558014.git.geert+renesas@glider.be
* clk: renesas: r8a779f0: Fix SD0H clock nameGeert Uytterhoeven2022-10-261-1/+1
| | | | | | | | | Correct the misspelled textual name of the SD0H clock. Fixes: 9b5dd1ff705c6854 ("clk: renesas: r8a779f0: Add SDH0 clock") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/1f682d338f133608f138ae87323707436ad8c748.1665558014.git.geert+renesas@glider.be
* clk: renesas: r9a07g043: Drop WDT2 clock and reset entryLad Prabhakar2022-10-261-5/+0
| | | | | | | | | | | WDT CH2 is specifically to check the operation of Cortex-M33 CPU and if used from CA55 CPU would result in an unexpected behaviour. Hence drop WDT2 clock and reset entries. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20221009231253.15592-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r9a07g044: Drop WDT2 clock and reset entryLad Prabhakar2022-10-261-6/+1
| | | | | | | | | | | WDT CH2 is specifically to check the operation of Cortex-M33 CPU and if used from CA55 CPU would result in an unexpected behaviour. Hence drop WDT2 clock and reset entries. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20221009231013.14791-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a779g0: Add TPU clockGeert Uytterhoeven2022-10-261-0/+1
| | | | | | | | | | Add the module clock used by the 16-Bit Timer Pulse Unit (TPU) on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/f2c1e2c5411b7bd6af726e6baf6e1efc354a7cdf.1665147497.git.geert+renesas@glider.be
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-03 21:59:53 +0000