summaryrefslogtreecommitdiffstats
path: root/src/mainboard/google/skyrim/variants/baseboard/gpio.c
Commit message (Collapse)AuthorAgeFilesLines
* mb/google/skyrim: Remove unused sleep GPIO tableKarthikeyan Ramasubramanian2023-04-051-11/+0
| | | | | | | | | | | | | | | On Skyrim, there isn't a need for a sleep GPIO table. Remove the TODO and filler table and function to reduce unnecessary function overhead. BUG=None BRANCH=Skyrim TEST=Build Skyrim BIOS image. Change-Id: Ia9d55a5e2295bb2e2c2957c4f5207362f616022c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
* mb/google/skyrim: override winterhold PCIe configMartin Roth2023-03-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | Winterhold boards populate either NVMe or eMMC, but not both. This means that there is always one link that is unpopulated. The PCIe configuration code takes longer to verify that a link is unpopulated than to just train the link, so this slows down the boot by roughly 80ms vs the case when the device is present. Not training the device at all lowers boot time by another 20ms, for a total of 100ms saved. Looking at the NVMe CLKREQ signal before initializing the ports allows us to identify which device is populated and only initialize that device. BUG=b:271569628 TEST=Boot Whiterun and eMMC or NVMe correctly work, boot time is lower. BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I0b87f5e968cd1c87e62a1c0fbdee1fc0723f655d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* mb/google/skyrim: Configure GPIO 67 as an unused GPIOMartin Roth2023-02-091-2/+2
| | | | | | | | | | | | | | | | | GPIO 67 is not currently used on skyrim, so set it as no-connect. Since it's now free for other purposes, make sure that the SPI-ROM-SHARING functionality is disabled. BUG=b:268330591 TEST=Examine registers after change Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id083baf41d25920eca09795453a01aac1d00d0f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/skyrim: use gpio.h includeFelix Held2022-12-101-1/+1
| | | | | | | | | | | | | | | | Replace the amdblocks/gpio.h and soc/gpio.h includes with the common gpio.h which will include soc/gpio.h which will include amdblocks/gpio.h in the AMD SoC case. Since baseboard/ec.h and indirectly baseboard/gpio.h files will get included in the DSDT, the soc/gpio.h includes in those aren't replaced with a gpio.h include for now. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib982e338b5c6bc145ec1a8f6dd75175a42dfb426 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70436 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Implement touchscreen power sequencingMatt DeVillier2022-10-301-2/+8
| | | | | | | | | | | | | | | | | | | | | | Assuming variants have a touchscreen by default, set the enable GPIO high and hold in reset during romstage, then release reset in ramstage. This will allow the touchscreen to make use of the runtime I2C detect feature (enabled in a subsequent commit) so that an ACPI device entry is created only for the touchscreen actually present. Variants/SKUs which do not have a touchscreen (if any) can use the romstage/ramstage GPIO override tables to set the associated enable/ reset GPIOs to NC. BUG=b:121309055 TEST=build/boot skyrim with rest of patch series Change-Id: Ic4d7ac8f951bb94da2216a24dc85a96275c9d449 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/skyrim/var/baseboard: Update gpio setting for touchscreen IRQFrank Wu2022-10-221-1/+1
| | | | | | | | | | | | | | | | The touchscreen IRQ has been configured as LEVEL_LOW in skyrim projects. Therefore, update the gpio.c to be consistent with the configuration. BUG=b:253506651, b:251367588 BRANCH=None TEST=FW_NAME=frostflow emerge-skyrim coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Iccfe5b01f10899c43151762e4730a05990afa602 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chao Gui <chaogui@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* mb/google/skyrim: Allow variants to override romstage GPIO tableMatt DeVillier2022-10-131-1/+7
| | | | | | | | | | | | | Switch from gpio_configure_pads() to gpio_configure_pads_with_override() so variants can override romstage GPIO defaults. Rename baseboard function and add an weak empty override function to be used by variants. Will be used for touchscreen power sequencing in a follow-on commit. Change-Id: I45586237919cd07a171beac57f3510e26338f67f Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/skyrim: Rename pcie_gpio_table to romstage_gpio_tableMatt DeVillier2022-09-281-5/+6
| | | | | | | | | | | | | Rename so table more indicative of when GPIOs are set, and so it can be used for more than just setting PCIe GPIOs. Rename the getter function to match. Change-Id: I285602209072247895c2cb0830f3faf675328757 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/skyrim: rename baseboard GPIO table getter for clarityMatt DeVillier2022-09-281-1/+1
| | | | | | | | | | | | | | Rename variant_base_gpio_table() to baseboard_gpio_table(), since the GPIO table comes from the baseboard, and is overridden by a separate table from the variant. Drop the __weak qualifier as this function is not overridden. Change-Id: Icebf7e11736929389227063039575a4c5ecf3840 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/skyrim/var/winterhold: Bug fix, modify GXTP7863 irq settingEricKY Cheng2022-09-261-1/+1
| | | | | | | | | | | | | Modify GXTP7863 generic.irq to generic.irq_gpio. BUG=b:245082617 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: Iaf6cc6010132d5b33b06909ceb1069115a911b48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/skyrim: Resolve boot behaviorJon Murphy2022-08-071-0/+2
| | | | | | | | | | | | | | | Move GPIO init for SSD_AUX_RESET_L to ensure that eMMC devices will be initialized in time for the nominal boot flow. BUG=b:237701972 TEST=Boots to OS BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I610966fd9d31581f15d8bcd51f8a116c27fd6311 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66461 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Enable fingerprint sensor in SkyrimMoises Garcia2022-06-291-1/+1
| | | | | | | | | | | | | | | | | Add fingerprint device and select UART_ACPI driver. Disable FPMCU until the proper boot segment initializes it. BUG=b:228271993 BRANCH=NONE TEST=Can add fingerprints and unlock the device using them. Signed-off-by: Moises Garcia <moisesgarcia@google.com> Change-Id: I71e1c7d654395284cdec43bb6e5f581e546da36a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65299 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/skyrim/var/skyrim: Add audio codec and amp supportIan Feng2022-06-071-1/+1
| | | | | | | | | | | | | | | | Add two combination: 1. ALC5682I-VS and ALC1019 2. NAU88L25 and MAX98360 BUG=b:227165780, b:228879074 TEST=emerge-skyrim coreboot chromeos-bootimage Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I36d7b5c4e88825ceaa6922d9e3bed366f55a0d81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/skyrim/var/skyrim: Add USB WWAN configurationKarthikeyan Ramasubramanian2022-05-121-1/+1
| | | | | | | | | | | | | | | | | | Add Fibcom FM101-GL USB WWAN configuration with the required power sequence as suggested in Fibocom FM101-GL Hardware Guide V1.0. BUG=b:227761300 TEST=Build and boot to OS in Skyrim. Ensure that the WWAN module is enumerated in the output of lsusb. localhost ~ # lsusb Bus 004 Device 003: ID 2cb7:01a2 Fibocom Wireless Inc. Fibocom FM101-GL Module Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I39f8e7204e31d9a4d093aacd838a18e6d2f44970 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64004 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Fix SD card power sequenceIan Feng2022-05-051-0/+2
| | | | | | | | | | | | | | Fix power sequence according to datasheet:GL9750S-OIY04 rev1.24. BUG=b:229181624 TEST=Build and boot to OS in Skyrim. Ensure that the SD Controller and SD Card are enumerated fine. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Iea729d43d10a3f8353b4fe540146d00975f4d422 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/skyrim: Configure SD_AUX_RESET_L signalIan Feng2022-04-271-1/+1
| | | | | | | | | | | | | | | | | Set native function (SD_AUX_RESET_L), and drive it high. BUG=b:229181624 TEST=Build and boot to OS in Skyrim. Ensure that the SD Controller and SD Card are enumerated fine. 02:00.0 SD Host controller: Genesys Logic, Inc GL9750 (rev 01) Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I03d88d90acc03cdebcb1e83ed2e799dda8b5b735 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/skyrim: Add Goodix touchscreenIan Feng2022-04-191-4/+4
| | | | | | | | | | | | | Add Goodix touchscreen according to the Programming Guide Rev.0.7 BUG=b:228907558 TEST=local build and tested with Goodix touch screen Change-Id: I35dd3ca76e9e0f17508bef46c90b53b4be5d0033 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63573 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Implement mb_set_up_early_espiRaul E Rangel2022-03-281-0/+23
| | | | | | | | | | | | | This will setup the eSPI GPIOs in bootblock right before eSPI init. BUG=b:226635441 TEST=build skyrim Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6ff32bf840aa4b757e98d876cbd4e2ba15a760da Reviewed-on: https://review.coreboot.org/c/coreboot/+/63094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/skyrim: Swap eSPI_CS_L and SOC_DISABLE_DISP_BLRaul E Rangel2022-03-281-10/+10
| | | | | | | | | | | | | | | | | The eSPI CS function only exists on AGPIO30. We will need to rework all boards to make eSPI function. I also fixed the comments on the other eSPI pins. BUG=b:226635441 TEST=Build skyrim Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib03c0a7dcad31d10dd4bad0d10a0184ab84aef9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/skyrim: Fix Backlight GPIOJon Murphy2022-03-231-1/+1
| | | | | | | | | | | | | | | Backlight GPIO was set to HIGH, when it should have been set LOW to enable the backlight in the embedded display. BUG=b:224618411 TEST=load on Skyrim proto1, observe backlight Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ife3335ca5a3c2517a6817fccf0544e5fcacb1f9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63003 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Enable tis_plat_irq_statusRaul E Rangel2022-03-181-1/+1
| | | | | | | | | | | | | | | This will fix: > [INFO ] Probing TPM I2C: tis_plat_irq_status() not implemented, wasting 20ms to wait on Cr50! BUG=b:224618411 TEST=Compile skyrim Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5add694506ad089adcc8961f101bf507bc39a522 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62873 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Configure WLANJon Murphy2022-03-101-3/+24
| | | | | | | | | | | | | | Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN. Mappping derived from Skyrim schematic. BUG=b:214412172 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I16e35b443f741d366589fefb7fd21863369d1ec2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/skyrim:Update GPIO 32Jon Murphy2022-03-101-1/+1
| | | | | | | | | | | | | | | GPIO 32 was not allocated correctly, updating to reflect the native function use of the pin BUG=b:214412172 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Idadd2a802b3244eba8ee83f80d8f10baebe4ca40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62717 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Enable AP <-> D2 communicationJon Murphy2022-02-281-0/+32
| | | | | | | | | | | | | | | | Configure D2 I2C and Interrupt GPIOs during the early initialization. Add devicetree configuration for D2 device and enable the required config items. BUG=b:214414776 TEST=Build Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I57b6d0e9da9935596e54b8eab400440e518b4523 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/skyrim: Add smihandlerJon Murphy2022-02-261-0/+11
| | | | | | | | | | | | | BUG=b:214415408 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Icc52182294bb3402463a0a70a5c67779c60dfe32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62045 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: First pass GPIO configuriation for SkyrimJon Murphy2022-02-251-1/+133
| | | | | | | | | | | | | BUG=b:214415401 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I60b3b3cd50eea1253df2ae3e0aea83bb89e54702 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62042 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Add stubs to configure GPIOsJon Murphy2022-02-241-0/+33
BUG=b:214415401 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ieeda9aa0c18b5befea67d2849bd4114da0c348a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62041 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-13 09:36:18 +0000