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path: root/drivers/clk/renesas
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* clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*Wolfram Sang2023-02-105-173/+13
* clk: renesas: r8a779g0: Add CAN-FD clocksGeert Uytterhoeven2023-01-261-0/+2
* clk: renesas: r8a779g0: Tidy up DMAC name on SYS-DMACKuninori Morimoto2023-01-261-2/+2
* clk: renesas: r8a779a0: Tidy up DMAC name on SYS-DMACKuninori Morimoto2023-01-261-2/+2
* clk: renesas: r8a779g0: Add custom clock for PLL2Geert Uytterhoeven2023-01-243-7/+164
* clk: renesas: cpg-mssr: Remove superfluous check in resume codeGeert Uytterhoeven2023-01-231-3/+2
* clk: renesas: r9a06g032: Handle h2mode setting based on USBF presenceHerve Codina2023-01-231-0/+28
* clk: renesas: cpg-mssr: Fix use after free if cpg_mssr_common_init() failedAlexey Khoroshilov2023-01-121-1/+2
* clk: renesas: r9a07g044: Add clock and reset entries for CRULad Prabhakar2023-01-121-1/+25
* clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entriesPhil Edworthy2022-12-271-0/+20
* clk: renesas: r9a09g011: Add USB clock and reset entriesBiju Das2022-12-271-0/+21
* clk: renesas: r9a09g011: Add TIM clock and reset entriesBiju Das2022-12-271-0/+22
* clk: renesas: r8a779g0: Add display related clocksTomi Valkeinen2022-12-261-0/+9
* clk: renesas: rcar-gen4: Restore PLL enum sort orderGeert Uytterhoeven2022-12-261-1/+1
* clk: renesas: r8a779g0: Fix OSC predividersGeert Uytterhoeven2022-12-261-4/+4
* clk: renesas: r9a09g011: Add PWM clock and reset entriesBiju Das2022-12-261-0/+10
* clk: renesas: r8a779f0: Fix Ethernet Switch clocksGeert Uytterhoeven2022-11-161-2/+2
* clk: renesas: r8a779g0: Add Z0 clock supportGeert Uytterhoeven2022-11-151-0/+1
* clk: renesas: r8a779g0: Add CMT clocksWolfram Sang2022-11-081-0/+4
* clk: renesas: r8a779g0: Add TMU and SASYNCRT clocksWolfram Sang2022-11-081-0/+6
* clk: renesas: r8a779f0: Fix SCIF parent clocksWolfram Sang2022-11-081-4/+4
* clk: renesas: r8a779f0: Fix HSCIF parent clocksWolfram Sang2022-11-081-4/+4
* clk: renesas: r9a06g032: Repair grave increment errorMarek Vasut2022-11-011-2/+1
* clk: renesas: rzg2l: Don't assume all CPG_MOD clocks support PMLad Prabhakar2022-10-282-15/+28
* clk: renesas: rzg2l: Fix typo in struct rzg2l_cpg_priv kerneldocLad Prabhakar2022-10-261-1/+1
* clk: renesas: r8a779a0: Fix SD0H clock nameWolfram Sang2022-10-261-1/+1
* clk: renesas: r8a779g0: Add RPC-IF clockGeert Uytterhoeven2022-10-261-1/+2
* clk: renesas: r8a779g0: Add SDHI clocksGeert Uytterhoeven2022-10-261-1/+3
* clk: renesas: r8a779f0: Add SASYNCPER internal clockGeert Uytterhoeven2022-10-261-3/+5
* clk: renesas: r8a779f0: Fix SD0H clock nameGeert Uytterhoeven2022-10-261-1/+1
* clk: renesas: r9a07g043: Drop WDT2 clock and reset entryLad Prabhakar2022-10-261-5/+0
* clk: renesas: r9a07g044: Drop WDT2 clock and reset entryLad Prabhakar2022-10-261-6/+1
* clk: renesas: r8a779g0: Add TPU clockGeert Uytterhoeven2022-10-261-0/+1
* clk: renesas: r8a779g0: Add PWM clockGeert Uytterhoeven2022-10-261-0/+1
* clk: renesas: r8a779g0: Add SCIF clocksGeert Uytterhoeven2022-10-261-0/+4
* Merge tag 'renesas-clk-fixes-for-v6.1-tag1'Geert Uytterhoeven2022-10-261-4/+9
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| * clk: renesas: r8a779g0: Fix HSCIF parent clocksGeert Uytterhoeven2022-10-261-4/+4
| * clk: renesas: r8a779g0: Add SASYNCPER clocksGeert Uytterhoeven2022-10-181-0/+5
* | clk: renesas: r9a07g044: Add MTU3a clock and reset entryBiju Das2022-10-171-1/+4
* | clk: renesas: r8a779g0: Add INTC-EX clockGeert Uytterhoeven2022-10-171-0/+1
* | clk: renesas: r8a779g0: Add MSIOF clocksGeert Uytterhoeven2022-10-171-0/+6
* | clk: renesas: r8a779g0: Add SYS-DMAC clocksGeert Uytterhoeven2022-10-171-0/+2
* | clk: renesas: r8a779f0: Add Ethernet Switch clocksYoshihiro Shimoda2022-10-171-0/+2
* | clk: renesas: rzg2l: Fix typo in function nameLad Prabhakar2022-10-171-3/+3
* | clk: renesas: rzg2l: Support sd clk mux round operationBiju Das2022-10-171-1/+1
|/
* clk: renesas: r8a779g0: Add EtherAVB clocksGeert Uytterhoeven2022-09-181-0/+3
* clk: renesas: r8a779g0: Add PFC/GPIO clocksGeert Uytterhoeven2022-09-181-0/+4
* clk: renesas: r8a779g0: Add I2C clocksGeert Uytterhoeven2022-09-181-0/+6
* clk: renesas: r8a779g0: Add watchdog clockGeert Uytterhoeven2022-09-181-0/+1
* clk: renesas: r8a779f0: Add MSIOF clocksWolfram Sang2022-08-291-0/+4