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* mb/google/byra/var/*: Set LAN device type back to pciMatt DeVillier2023-11-211-1/+1
| | | | | | | | | | | | | | | This partially reverts commit f493857c9bc1 ("mb/google/brya/var/*: Set dGPU/LAN/WLAN device type to generic"). Setting the LAN device type to generic broke programming the LAN MAC address, so set it back to pci. TEST=build/boot google/brya (osiris), verify LAN MAC address programmed correctly. Change-Id: I4fb43b7212e67b5c38724baad572860bc45b558e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79150 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/*: Set dGPU/LAN/WLAN device type to genericMatt DeVillier2023-11-031-2/+2
| | | | | | | | | | | | | | | | | Change the dGPU/LAN/WiFi device types from PCI to generic, so that the bogus PCI device and function values don't end up in coreboot's internal device tree. The presence of these bogus PCI devices cause the LPI constraint generator to create does a reference for an ACPI device which does not exist (SB.PCI0.RP{xx}.MCHC). The invalid reference(s) cause a Windows BSOD (INTERNAL_POWER_ERROR). TEST=untested Change-Id: Ic997b5ad893853b99ae53a2e5c7acf58467ea4f1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78873 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/agah: Adjust i2c1 and i2c2 timing Parameters for 400KHzTarun Tuli2023-02-151-0/+6
| | | | | | | | | | | | | | | | | Adjust timing parameters on i2c1 and i2c2 to meet timing requirements. For SCL, the t-high time is now over the min 600ns requirement for 400KHz operation (measure at over 700ns). Also, this change does not violate other parameters - rise time, setup time and hold time. BUG=b:264704732 TEST=Verified all timings meet spec now Change-Id: I0e92b2c9c25e7fb5fa7082af3f4a88da168c3ef2 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya: Add ACPI DmaProperty for ethernet devicesKapil Porwal2022-11-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ACPI DmaProperty for ethernet devices. BUG=b:259716145 TEST=Verified SSDT on google/osiris. Before: Scope (\_SB.PCI0.RP01) { Device (RLTK) { Name (_HID, "R8168") // _HID: Hardware ID Name (_UID, 0xD0E889DD) // _UID: Unique ID Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name Name (_ADR, 0x00000000) // _ADR: Address Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x07, 0x03 }) } } After: Scope (\_SB.PCI0.RP01) { Device (RLTK) { Name (_HID, "R8168") // _HID: Hardware ID Name (_UID, 0xD0E889DD) // _UID: Unique ID Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name Name (_ADR, 0x00000000) // _ADR: Address Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x07, 0x03 }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } }) } } Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I647593fd02644d30cd21b60d8305c0ec55dc64cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/70017 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/*/{device,override}tree: Set touchpads to use detect (vs probed) flagMatt DeVillier2022-09-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Historically, ChromeOS devices have worked around the problem of OEMs using several different parts for touchpads/touchscreens by using a ChromeOS kernel-specific 'probed' flag (rejected by the upstream kernel) to indicate that the device may or may not be present, and that the driver should probe to confirm device presence. Since c636142b, coreboot now supports detection for i2c devices at runtime when creating the device entries for the ACPI/SSDT tables, rendering the 'probed' flag obsolete for touchpads. Switch all touchpads in the tree from using the 'probed' flag to the 'detect' flag. Touchscreens require more involved power sequencing, which will be done at some future time, after which they will switch over as well. TEST: build/boot at least one variant for each baseboard in the tree. Verify touchpad works under Linux and Windows. Verify only a single touchpad device is present in the ACPI tables. Change-Id: I47c6eed37eb34c044e27963532e544d3940a7c15 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67305 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/agah: Reenable ASPM L1 substatesTim Wawrzynczak2022-08-241-1/+0
| | | | | | | | | | | | | | | | Now that the GPU CLKREQ# signal is working correctly, ASPM L1 substates can be enabled and appear functional. BUG=b:240390998 TEST=lspci reports them as functional, MODS does not hang Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I8297f6bbf7f5a1f7d4ac519bc5b7b3112a74a9a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66811 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/agah: Enable DPTF oem_variablesTony Huang2022-08-241-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Support oem_variables and change based on EC notify event. BUG=b:238921409 TEST=emerge-draco coreboot 1. check ACPI object ODVX has oem_variable[0]=0 Name (ODVX, Package (0x06) { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } 2. check can get EC oem variable change notify in the kernel log Change-Id: Ibd856563a43d73a3b1be09b3fbebca1b36b5eab1 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66575 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/variants/agah: update dptf settingTony Huang2022-08-071-8/+46
| | | | | | | | | | | | | | | | 1. Add active policy 2. Set critical policy trigger point to 105C 3. Correct TSR location BUG=b:240634844 TEST=emerge-draco coreboot values provided and verified by thermal team Change-Id: I0d91bad03cbdeea5c84b533580ac98072ce0110b Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* mb/google/brya/variants/agah: set tcc_offset to 3Tony Huang2022-08-031-0/+1
| | | | | | | | | | | | | | | | Set tcc_offset value to 3 in devicetree for Thermal Control Circuit (TCC) activation feature. This value is suggested by Thermal team. BUG=b:240600260 TEST=emerge-draco coreboot verified by thermal team Change-Id: I3044643d52f1d6e883beb3ec87a77f32d086f46c Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* mb/google/brya/var/agah: Update ASPM settings for dGPUTim Wawrzynczak2022-07-281-1/+1
| | | | | | | | | | | | | | | | | | After some debugging, it has been determined that the ASPM L0s substate is functional, but there is still some problem with ASPM L1 substates, so this patch updates ASPM status for the dGPU from disabled to L0s only. BUG=b:240390998 TEST=tested with nvidia tools Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I584bdbf26eda20246034263446492bf4daf5f3b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/agah: Adjust I2C speedTony Huang2022-07-201-0/+9
| | | | | | | | | | | | | Adjust I2C speed for codec, TPM, touchpad. BUG=b:237691531 TEST=Built and verified adjusted I2C speed < 400KHz Change-Id: I203d137d61019235ddf38ef74607427db2a7e975 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/agah: Disable ASPM for dGPUTim Wawrzynczak2022-07-151-0/+1
| | | | | | | | | | | | | | Since ASPM is not verified as fully functional yet, and the board is still in development, this patch disables ASPM for the dGPU. BUG=b:236676400 TEST=boot to OS in agah, lspci -vvv shows ASPM is disabled Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I525eeb18c57d45fd55335b63a59262066afc9567 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* mb/google/brya/var/agah: Disable thunderbolt interfaceTony Huang2022-07-121-0/+6
| | | | | | | | | | | | | | Agah doesn't support TBT interface so disable it in devicetree, for fitimage configuration is at chrome-internal:4846869. BUG=b:224423318 TEST=Build and check DUT boots. Change-Id: I1eb43e86de5debf24ebde6eace14fe04bad5e5b1 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65699 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya: Disable SaGV support for agah variantAnil Kumar2022-07-071-1/+1
| | | | | | | | | | | | | | | | | | | | agah proto boards with i7 silicon face boot issues due to high power consumption during MRC training. This patch is a temporary WA to run in SAGV disabled mode while the thermal issue is being investigated. BUG=b:234402102 BRANCH=firmware-brya-14505.B TEST=Build CB image and boot on agah board. Change-Id: I431d233b23fb4f5c68117ea380fdec5646b88346 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65300 Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* mb/google/brya/var/agah: Remove stop pin declaration for LANTony Huang2022-06-171-4/+1
| | | | | | | | | | | | | | | | | | | | Currently, the system fails to enter S0ix as the stop pin declation for LAN device will prevent system from entering suspend. So remove the stop pin declaration. Also add device_index=0 for the first NIC to get correct MAC from VPD setting. BUG=b:210970640 TEST=Build and suspend_stress_test -c 20 pass Check LAN works fine after resume Change-Id: I513bf8b4bcb4d6db2eed2790fef7f6000a441274 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65123 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/agah: Correct _PLD valuesWon Chung2022-06-141-8/+8
| | | | | | | | | | | | | | | | | | | | | | | This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ A2 | | A0 C2 | | C0 | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I8cc7be20988ff3cc3be1fac3c9b143059ff9190c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65088 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/agah: Use USB2_PORT_MAX_TYPE_C for Type-C USB2 portIvy Jian2022-06-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | Override the type-C USB2 port setting from `USB2_PORT_TYPE_C` to `USB2_PORT_MAX_TYPE_C`. The change is required to detect USB2 device on type-C port of Agah boards. BUG=b:233554817 TEST=build and test USB2 hub could be detected on both the Type-C ports. ================================================================= usb 3-3: New USB device found,idVendor=1a40,idProduct=0801,bcdDevice= 1.00 usb 3-3: New USB device strings: Mfr=0, Product=1, SerialNumber=0 usb 3-3: Product: USB 2.0 Hub hub 3-3:1.0: USB hub found hub 3-3:1.0: 4 ports detected ================================================================= Change-Id: I856402aa128db0c4ba092e1c2a66e29bc9165c40 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64988 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/agah: Update USB-C port settingIvy Jian2022-05-281-2/+2
| | | | | | | | | | | | | | | | | Correct the USB-C port setting according to schematics. AP log: port C0 DISC req: usage 1 usb3 3 usb2 1 port C1 DISC req: usage 1 usb3 1 usb2 3 BUG=b:233554817 BRANCH=brya TEST=emerge-draco coreboot chromeos-bootimage Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: Iea4aee19dff8e0bc863be46532f89e81f52f281b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/var/agah: Enable PCIe RP 3 for LANTony Huang2022-05-121-0/+6
| | | | | | | | | | | | | | | Using CLKREQ 4 and CLKSRC 4 BUG=b:210970640 BRANCH=NONE TEST=emerge-draco coreboot chromeos-bootimage Change-Id: Ie0e362013551036a03ef69a98c6f1793e0e75c41 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/agah: Add GPU power sequencingTim Wawrzynczak2022-05-051-0/+9
| | | | | | | | | | | | | | | | | | This patch adds support for power sequencing of the Nvidia GN3050 for agah, which uses PCH GPIOs to control the 5 power rails required for the GPU. The GPU is power sequenced on during mainboard initialization, then it is enumerated on the PCI bus and its resources are assigned. This GPU will be used in a sort of "hybrid graphics" mode, therefore during finalization, since its PCI BARs are saved into ACPI memory and the GPU is not required upon initial boot, the GPU is power sequenced off. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1072be12ef58af5859e2a2d19c4a9c1adc0b0f88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/var/agah: Change Aux settings to TCSS port 2Tony Huang2022-04-291-2/+2
| | | | | | | | | | | | | | | | Agah USB-C port 0 is non-retimer port and it connects to TCSS port 2. Bit[5:4] is for TCSS Port 2, so re-configure "TcssAuxOri" to 0x10 and "typec_aux_bias_pads" to 2 to correct the port. BUG=b:210970640 BRANCH=NONE TEST=emerge-draco coreboot chromeos-bootimage Change-Id: I2d26777e850187aee0b676de13dff915474fed7b Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/agah: Replace amp max98390 with max98360Tony Huang2022-03-311-22/+9
| | | | | | | | | | | | | | | | Based on the latest schematic, agah will replace the Maxim 98390 speaker amps with Maxim max98360. This patch updates the devicetree entries to reflect that. BUG=b:210970640 BRANCH=brya TEST=emerge-draco coreboot Change-Id: I7ea36d276f7ffeae1510483027092e2bc59690fc Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/adl/chip.h: Convert all camel case variables to snake caseMAULIK V VAGHELA2022-03-151-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | coreboot chip.h files mainly contains variable which allows board to fill platform configuration through devicetree. Since many of this configuration involves FSP UPDs, variable names were in camel case which aligned with UPD naming convention. By default coreboot follow snake case variable naming, so cleaning up file to align all variable names as per coreboot convention. During renaming process, this patch also removes unused variables listed below: -> SataEnable // Checked in SoC code based on PCI dev enabled status -> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used Note: Since separating out changes into smaller CL might break the compilation for the patch set, this is being pushed as a single big CL. BUG=None BRANCH=firmware-brya-14505.B TEST=All boards using ADL SoC compiles with the CL. Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/agah: Use ACPI _PLD macroSubrata Banik2022-02-181-8/+16
| | | | | | | | | | | | | This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Idb8f30b2d1069aea1d5ce7c5dda7f99de33a7c26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61803 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/agah: Fix PLD group orderSubrata Banik2022-02-181-7/+7
| | | | | | | | | | | | | | | | | In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9cef57bbaf3e3519b7f6a7e3d86979722b598ad7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/agah: Change ELAN touchpad driver for eKT3744Tony Huang2022-02-161-9/+7
| | | | | | | | | | | | | Change to use i2c/generic to match ELAN FW update script. BUG=b:210970640 TEST=emerge-draco coreboot chromeos-bootimage Change-Id: Ib416da6000d9e99f9c37cf497fb1c43e3fca0220 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/agah: Update Aux settingsTony Huang2022-02-121-1/+4
| | | | | | | | | | | | | | | | | Agah port 0 does not have a retimer so the port needs to be configured for the SOC to handle Aux orientation flipping. Add the "TcssAuxOri" and "typec_aux_bias_pads" to lets the SoC IOM firmware control the Aux DC bias voltages. BUG=b:210970640 BRANCH=NONE TEST=emerge-draco coreboot chromeos-bootimage Change-Id: I1fa5c4574b1a0e8dd2f66f3f6382436337c530fa Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/agah: update overridetreeTony Huang2022-01-141-1/+284
| | | | | | | | | | | | | Init basic override devicetree based on initial schematics BUG=b:210970640 TEST=emerge-brya coreboot Change-Id: I7b7badacce27dd7da4f138c6f2465af518715e7f Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60837 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya: Create agah variantTony Huang2022-01-061-0/+6
Create the agah variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:210970640 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_AGAH Change-Id: I6adcf4e8010969cf185513d68bb1b76ea08194c7 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-16 23:33:36 +0000